* [PATCH AUTOSEL 6.1 22/53] perf/x86/cstate: Add Meteor Lake support
[not found] <20230116140154.114951-1-sashal@kernel.org>
@ 2023-01-16 14:01 ` Sasha Levin
2023-01-16 14:01 ` [PATCH AUTOSEL 6.1 23/53] perf/x86/msr: " Sasha Levin
` (2 subsequent siblings)
3 siblings, 0 replies; 4+ messages in thread
From: Sasha Levin @ 2023-01-16 14:01 UTC (permalink / raw)
To: linux-kernel, stable
Cc: Kan Liang, Ingo Molnar, Andi Kleen, Sasha Levin, peterz, mingo,
acme, tglx, bp, dave.hansen, x86, linux-perf-users
From: Kan Liang <kan.liang@linux.intel.com>
[ Upstream commit 01f2ea5bcf89dbd7a6530dbce7f2fb4e327e7006 ]
Meteor Lake is Intel's successor to Raptor lake. From the perspective of
Intel cstate residency counters, there is nothing changed compared with
Raptor lake.
Share adl_cstates with Raptor lake.
Update the comments for Meteor Lake.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Reviewed-by: Andi Kleen <ak@linux.intel.com>
Link: https://lore.kernel.org/r/20230104201349.1451191-6-kan.liang@linux.intel.com
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
arch/x86/events/intel/cstate.c | 21 ++++++++++++---------
1 file changed, 12 insertions(+), 9 deletions(-)
diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c
index a2834bc93149..3019fb1926e3 100644
--- a/arch/x86/events/intel/cstate.c
+++ b/arch/x86/events/intel/cstate.c
@@ -41,6 +41,7 @@
* MSR_CORE_C1_RES: CORE C1 Residency Counter
* perf code: 0x00
* Available model: SLM,AMT,GLM,CNL,ICX,TNT,ADL,RPL
+ * MTL
* Scope: Core (each processor core has a MSR)
* MSR_CORE_C3_RESIDENCY: CORE C3 Residency Counter
* perf code: 0x01
@@ -51,50 +52,50 @@
* perf code: 0x02
* Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,
* SKL,KNL,GLM,CNL,KBL,CML,ICL,ICX,
- * TGL,TNT,RKL,ADL,RPL,SPR
+ * TGL,TNT,RKL,ADL,RPL,SPR,MTL
* Scope: Core
* MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter
* perf code: 0x03
* Available model: SNB,IVB,HSW,BDW,SKL,CNL,KBL,CML,
- * ICL,TGL,RKL,ADL,RPL
+ * ICL,TGL,RKL,ADL,RPL,MTL
* Scope: Core
* MSR_PKG_C2_RESIDENCY: Package C2 Residency Counter.
* perf code: 0x00
* Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL,
* KBL,CML,ICL,ICX,TGL,TNT,RKL,ADL,
- * RPL,SPR
+ * RPL,SPR,MTL
* Scope: Package (physical package)
* MSR_PKG_C3_RESIDENCY: Package C3 Residency Counter.
* perf code: 0x01
* Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL,
* GLM,CNL,KBL,CML,ICL,TGL,TNT,RKL,
- * ADL,RPL
+ * ADL,RPL,MTL
* Scope: Package (physical package)
* MSR_PKG_C6_RESIDENCY: Package C6 Residency Counter.
* perf code: 0x02
* Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,
* SKL,KNL,GLM,CNL,KBL,CML,ICL,ICX,
- * TGL,TNT,RKL,ADL,RPL,SPR
+ * TGL,TNT,RKL,ADL,RPL,SPR,MTL
* Scope: Package (physical package)
* MSR_PKG_C7_RESIDENCY: Package C7 Residency Counter.
* perf code: 0x03
* Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,CNL,
- * KBL,CML,ICL,TGL,RKL,ADL,RPL
+ * KBL,CML,ICL,TGL,RKL,ADL,RPL,MTL
* Scope: Package (physical package)
* MSR_PKG_C8_RESIDENCY: Package C8 Residency Counter.
* perf code: 0x04
* Available model: HSW ULT,KBL,CNL,CML,ICL,TGL,RKL,
- * ADL,RPL
+ * ADL,RPL,MTL
* Scope: Package (physical package)
* MSR_PKG_C9_RESIDENCY: Package C9 Residency Counter.
* perf code: 0x05
* Available model: HSW ULT,KBL,CNL,CML,ICL,TGL,RKL,
- * ADL,RPL
+ * ADL,RPL,MTL
* Scope: Package (physical package)
* MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter.
* perf code: 0x06
* Available model: HSW ULT,KBL,GLM,CNL,CML,ICL,TGL,
- * TNT,RKL,ADL,RPL
+ * TNT,RKL,ADL,RPL,MTL
* Scope: Package (physical package)
*
*/
@@ -686,6 +687,8 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {
X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE, &adl_cstates),
X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_P, &adl_cstates),
X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_S, &adl_cstates),
+ X86_MATCH_INTEL_FAM6_MODEL(METEORLAKE, &adl_cstates),
+ X86_MATCH_INTEL_FAM6_MODEL(METEORLAKE_L, &adl_cstates),
{ },
};
MODULE_DEVICE_TABLE(x86cpu, intel_cstates_match);
--
2.35.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH AUTOSEL 6.1 23/53] perf/x86/msr: Add Meteor Lake support
[not found] <20230116140154.114951-1-sashal@kernel.org>
2023-01-16 14:01 ` [PATCH AUTOSEL 6.1 22/53] perf/x86/cstate: Add Meteor Lake support Sasha Levin
@ 2023-01-16 14:01 ` Sasha Levin
2023-01-16 14:01 ` [PATCH AUTOSEL 6.1 24/53] perf/x86/msr: Add Emerald Rapids Sasha Levin
2023-01-16 14:01 ` [PATCH AUTOSEL 6.1 25/53] perf/x86/intel/uncore: " Sasha Levin
3 siblings, 0 replies; 4+ messages in thread
From: Sasha Levin @ 2023-01-16 14:01 UTC (permalink / raw)
To: linux-kernel, stable
Cc: Kan Liang, Ingo Molnar, Andi Kleen, Sasha Levin, peterz, mingo,
acme, tglx, bp, dave.hansen, x86, linux-perf-users
From: Kan Liang <kan.liang@linux.intel.com>
[ Upstream commit 6887a4d3aede084bf08b70fbc9736c69fce05d7f ]
Meteor Lake is Intel's successor to Raptor lake. PPERF and SMI_COUNT MSRs
are also supported.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Reviewed-by: Andi Kleen <ak@linux.intel.com>
Link: https://lore.kernel.org/r/20230104201349.1451191-7-kan.liang@linux.intel.com
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
arch/x86/events/msr.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c
index ecced3a52668..074150d28fa8 100644
--- a/arch/x86/events/msr.c
+++ b/arch/x86/events/msr.c
@@ -107,6 +107,8 @@ static bool test_intel(int idx, void *data)
case INTEL_FAM6_RAPTORLAKE:
case INTEL_FAM6_RAPTORLAKE_P:
case INTEL_FAM6_RAPTORLAKE_S:
+ case INTEL_FAM6_METEORLAKE:
+ case INTEL_FAM6_METEORLAKE_L:
if (idx == PERF_MSR_SMI || idx == PERF_MSR_PPERF)
return true;
break;
--
2.35.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH AUTOSEL 6.1 24/53] perf/x86/msr: Add Emerald Rapids
[not found] <20230116140154.114951-1-sashal@kernel.org>
2023-01-16 14:01 ` [PATCH AUTOSEL 6.1 22/53] perf/x86/cstate: Add Meteor Lake support Sasha Levin
2023-01-16 14:01 ` [PATCH AUTOSEL 6.1 23/53] perf/x86/msr: " Sasha Levin
@ 2023-01-16 14:01 ` Sasha Levin
2023-01-16 14:01 ` [PATCH AUTOSEL 6.1 25/53] perf/x86/intel/uncore: " Sasha Levin
3 siblings, 0 replies; 4+ messages in thread
From: Sasha Levin @ 2023-01-16 14:01 UTC (permalink / raw)
To: linux-kernel, stable
Cc: Kan Liang, Ingo Molnar, Sasha Levin, peterz, mingo, acme, tglx,
bp, dave.hansen, x86, linux-perf-users
From: Kan Liang <kan.liang@linux.intel.com>
[ Upstream commit 69ced4160969025821f2999ff92163ed26568f1c ]
The same as Sapphire Rapids, the SMI_COUNT MSR is also supported on
Emerald Rapids. Add Emerald Rapids model.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Link: https://lore.kernel.org/r/20230106160449.3566477-3-kan.liang@linux.intel.com
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
arch/x86/events/msr.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c
index 074150d28fa8..c65d8906cbcf 100644
--- a/arch/x86/events/msr.c
+++ b/arch/x86/events/msr.c
@@ -69,6 +69,7 @@ static bool test_intel(int idx, void *data)
case INTEL_FAM6_BROADWELL_G:
case INTEL_FAM6_BROADWELL_X:
case INTEL_FAM6_SAPPHIRERAPIDS_X:
+ case INTEL_FAM6_EMERALDRAPIDS_X:
case INTEL_FAM6_ATOM_SILVERMONT:
case INTEL_FAM6_ATOM_SILVERMONT_D:
--
2.35.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH AUTOSEL 6.1 25/53] perf/x86/intel/uncore: Add Emerald Rapids
[not found] <20230116140154.114951-1-sashal@kernel.org>
` (2 preceding siblings ...)
2023-01-16 14:01 ` [PATCH AUTOSEL 6.1 24/53] perf/x86/msr: Add Emerald Rapids Sasha Levin
@ 2023-01-16 14:01 ` Sasha Levin
3 siblings, 0 replies; 4+ messages in thread
From: Sasha Levin @ 2023-01-16 14:01 UTC (permalink / raw)
To: linux-kernel, stable
Cc: Kan Liang, Ingo Molnar, Sasha Levin, peterz, mingo, acme, tglx,
bp, dave.hansen, x86, linux-perf-users
From: Kan Liang <kan.liang@linux.intel.com>
[ Upstream commit 5268a2842066c227e6ccd94bac562f1e1000244f ]
From the perspective of the uncore PMU, the new Emerald Rapids is the
same as the Sapphire Rapids. The only difference is the event list,
which will be supported in the perf tool later.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Link: https://lore.kernel.org/r/20230106160449.3566477-4-kan.liang@linux.intel.com
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
arch/x86/events/intel/uncore.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/events/intel/uncore.c b/arch/x86/events/intel/uncore.c
index 6f1ccc57a692..459b1aafd4d4 100644
--- a/arch/x86/events/intel/uncore.c
+++ b/arch/x86/events/intel/uncore.c
@@ -1833,6 +1833,7 @@ static const struct x86_cpu_id intel_uncore_match[] __initconst = {
X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_P, &adl_uncore_init),
X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_S, &adl_uncore_init),
X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, &spr_uncore_init),
+ X86_MATCH_INTEL_FAM6_MODEL(EMERALDRAPIDS_X, &spr_uncore_init),
X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D, &snr_uncore_init),
{},
};
--
2.35.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
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2023-01-16 14:01 ` [PATCH AUTOSEL 6.1 22/53] perf/x86/cstate: Add Meteor Lake support Sasha Levin
2023-01-16 14:01 ` [PATCH AUTOSEL 6.1 23/53] perf/x86/msr: " Sasha Levin
2023-01-16 14:01 ` [PATCH AUTOSEL 6.1 24/53] perf/x86/msr: Add Emerald Rapids Sasha Levin
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