From: Ian Rogers <irogers@google.com>
To: Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Jiri Olsa <jolsa@kernel.org>, Namhyung Kim <namhyung@kernel.org>,
Zhengjun Xing <zhengjun.xing@linux.intel.com>,
Kan Liang <kan.liang@linux.intel.com>,
linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org,
Edward Baker <edward.baker@intel.com>,
Dan Williams <dan.j.williams@intel.com>,
perry.taylor@intel.com, caleb.biggers@intel.com,
samantha.alt@intel.com, weilin.wang@intel.com
Cc: Ian Rogers <irogers@google.com>
Subject: [PATCH v2 7/9] perf vendor events: Sandybridge v19 events
Date: Thu, 23 Mar 2023 12:20:26 -0700 [thread overview]
Message-ID: <20230323192028.135759-8-irogers@google.com> (raw)
In-Reply-To: <20230323192028.135759-1-irogers@google.com>
Adds BR_MISP_EXEC.INDIRECT event.
Signed-off-by: Ian Rogers <irogers@google.com>
---
tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +-
tools/perf/pmu-events/arch/x86/sandybridge/pipeline.json | 8 ++++++++
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv
index e41c289fa427..41d755d570e6 100644
--- a/tools/perf/pmu-events/arch/x86/mapfile.csv
+++ b/tools/perf/pmu-events/arch/x86/mapfile.csv
@@ -21,7 +21,7 @@ GenuineIntel-6-(57|85),v10,knightslanding,core
GenuineIntel-6-A[AC],v1.01,meteorlake,core
GenuineIntel-6-1[AEF],v3,nehalemep,core
GenuineIntel-6-2E,v3,nehalemex,core
-GenuineIntel-6-2A,v18,sandybridge,core
+GenuineIntel-6-2A,v19,sandybridge,core
GenuineIntel-6-(8F|CF),v1.11,sapphirerapids,core
GenuineIntel-6-(37|4A|4C|4D|5A),v15,silvermont,core
GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v55,skylake,core
diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/pipeline.json b/tools/perf/pmu-events/arch/x86/sandybridge/pipeline.json
index 54454e5e262c..ecaf94ccc9c7 100644
--- a/tools/perf/pmu-events/arch/x86/sandybridge/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/sandybridge/pipeline.json
@@ -210,6 +210,14 @@
"SampleAfterValue": "200003",
"UMask": "0xc4"
},
+ {
+ "BriefDescription": "Speculative mispredicted indirect branches",
+ "EventCode": "0x89",
+ "EventName": "BR_MISP_EXEC.INDIRECT",
+ "PublicDescription": "Counts speculatively miss-predicted indirect branches at execution time. Counts for indirect near CALL or JMP instructions (RET excluded).",
+ "SampleAfterValue": "200003",
+ "UMask": "0xe4"
+ },
{
"BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches.",
"EventCode": "0x89",
--
2.40.0.348.gf938b09366-goog
next prev parent reply other threads:[~2023-03-23 19:22 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-23 19:20 [PATCH v2 0/9] Update Intel events and make optane events dynamic Ian Rogers
2023-03-23 19:20 ` [PATCH v2 4/9] perf vendor events: Haswell v33 events Ian Rogers
2023-03-23 19:20 ` [PATCH v2 5/9] perf vendor events: Haswellx v27 events Ian Rogers
2023-03-23 19:20 ` [PATCH v2 6/9] perf vendor events: Jaketown v23 events Ian Rogers
2023-03-23 19:20 ` Ian Rogers [this message]
2023-03-23 19:20 ` [PATCH v2 8/9] perf metrics: Add has_optane literal Ian Rogers
2023-03-23 20:31 ` Liang, Kan
2023-03-23 20:43 ` Dan Williams
2023-03-24 7:15 ` Ian Rogers
2023-03-23 19:20 ` [PATCH v2 9/9] perf vendor events: Update metrics to detect optane memory at runtime Ian Rogers
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