[PATCH v2 5/5] perf vendor events intel: Update free running tigerlake events

[Ian Rogers <irogers@google.com>]

Fix the topic, PMU name, event code and umask.

These updates were generated by:
https://github.com/intel/perfmon/blob/main/scripts/create_perf_json.py
with this PR:
https://github.com/intel/perfmon/pull/66

Signed-off-by: Ian Rogers <irogers@google.com>
---
 .../arch/x86/tigerlake/uncore-memory.json     | 50 +++++++++++++++++++
 .../arch/x86/tigerlake/uncore-other.json      | 36 -------------
 2 files changed, 50 insertions(+), 36 deletions(-)
 create mode 100644 tools/perf/pmu-events/arch/x86/tigerlake/uncore-memory.json

diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/uncore-memory.json b/tools/perf/pmu-events/arch/x86/tigerlake/uncore-memory.json
new file mode 100644
index 000000000000..99fb5259fd25
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/tigerlake/uncore-memory.json
@@ -0,0 +1,50 @@
+[
+    {
+        "BriefDescription": "Counts every read (RdCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.",
+        "EventCode": "0xff",
+        "EventName": "UNC_MC0_RDCAS_COUNT_FREERUN",
+        "PerPkg": "1",
+        "UMask": "0x20",
+        "Unit": "imc_free_running_0"
+    },
+    {
+        "BriefDescription": "Counts every 64B read and write request entering the Memory Controller to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.",
+        "EventCode": "0xff",
+        "EventName": "UNC_MC0_TOTAL_REQCOUNT_FREERUN",
+        "PerPkg": "1",
+        "UMask": "0x10",
+        "Unit": "imc_free_running_0"
+    },
+    {
+        "BriefDescription": "Counts every write (WrCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.",
+        "EventCode": "0xff",
+        "EventName": "UNC_MC0_WRCAS_COUNT_FREERUN",
+        "PerPkg": "1",
+        "UMask": "0x30",
+        "Unit": "imc_free_running_0"
+    },
+    {
+        "BriefDescription": "Counts every read (RdCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.",
+        "EventCode": "0xff",
+        "EventName": "UNC_MC1_RDCAS_COUNT_FREERUN",
+        "PerPkg": "1",
+        "UMask": "0x20",
+        "Unit": "imc_free_running_1"
+    },
+    {
+        "BriefDescription": "Counts every 64B read and write request entering the Memory Controller to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.",
+        "EventCode": "0xff",
+        "EventName": "UNC_MC1_TOTAL_REQCOUNT_FREERUN",
+        "PerPkg": "1",
+        "UMask": "0x10",
+        "Unit": "imc_free_running_1"
+    },
+    {
+        "BriefDescription": "Counts every write (WrCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.",
+        "EventCode": "0xff",
+        "EventName": "UNC_MC1_WRCAS_COUNT_FREERUN",
+        "PerPkg": "1",
+        "UMask": "0x30",
+        "Unit": "imc_free_running_1"
+    }
+]
diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/uncore-other.json b/tools/perf/pmu-events/arch/x86/tigerlake/uncore-other.json
index a5a254327ae9..6e43aaf64e28 100644
--- a/tools/perf/pmu-events/arch/x86/tigerlake/uncore-other.json
+++ b/tools/perf/pmu-events/arch/x86/tigerlake/uncore-other.json
@@ -93,41 +93,5 @@
         "EventName": "UNC_CLOCK.SOCKET",
         "PerPkg": "1",
         "Unit": "CLOCK"
-    },
-    {
-        "BriefDescription": "Counts every read (RdCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.",
-        "EventName": "UNC_MC0_RDCAS_COUNT_FREERUN",
-        "PerPkg": "1",
-        "Unit": "imc"
-    },
-    {
-        "BriefDescription": "Counts every 64B read and write request entering the Memory Controller to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.",
-        "EventName": "UNC_MC0_TOTAL_REQCOUNT_FREERUN",
-        "PerPkg": "1",
-        "Unit": "imc"
-    },
-    {
-        "BriefDescription": "Counts every write (WrCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.",
-        "EventName": "UNC_MC0_WRCAS_COUNT_FREERUN",
-        "PerPkg": "1",
-        "Unit": "imc"
-    },
-    {
-        "BriefDescription": "Counts every read (RdCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.",
-        "EventName": "UNC_MC1_RDCAS_COUNT_FREERUN",
-        "PerPkg": "1",
-        "Unit": "imc"
-    },
-    {
-        "BriefDescription": "Counts every 64B read and write request entering the Memory Controller to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.",
-        "EventName": "UNC_MC1_TOTAL_REQCOUNT_FREERUN",
-        "PerPkg": "1",
-        "Unit": "imc"
-    },
-    {
-        "BriefDescription": "Counts every write (WrCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.",
-        "EventName": "UNC_MC1_WRCAS_COUNT_FREERUN",
-        "PerPkg": "1",
-        "Unit": "imc"
     }
 ]
-- 
2.40.0.577.gac1e443424-goog