From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8AD8FC761A6 for ; Fri, 7 Apr 2023 00:14:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238384AbjDGAOa (ORCPT ); Thu, 6 Apr 2023 20:14:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34444 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238876AbjDGAOT (ORCPT ); Thu, 6 Apr 2023 20:14:19 -0400 Received: from mail-yw1-x1149.google.com (mail-yw1-x1149.google.com [IPv6:2607:f8b0:4864:20::1149]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 92E7893C5 for ; Thu, 6 Apr 2023 17:14:10 -0700 (PDT) Received: by mail-yw1-x1149.google.com with SMTP id 00721157ae682-54c0b8ca2d1so40902237b3.17 for ; Thu, 06 Apr 2023 17:14:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; t=1680826449; h=content-transfer-encoding:to:from:subject:references:mime-version :message-id:in-reply-to:date:from:to:cc:subject:date:message-id :reply-to; bh=KeEmcDWFc/SldpK/ezWRwN2cNjE5XRErQ4PS7868Kmc=; b=JH1VZd8NXBfh9XvitufpYei+L0XQV5Bhb/yu81WKaTZARygssirI5D9AWO5ocdDmO7 J5Bb+Bz2JCD74my86oOX5BuxPQHnDNaFesMn1xiXDBs+RYh4F3oHWhlyS3xz4SIurfO2 4NeDceV1p89xSHl38yGGlkiso7kvIzqGPgOsoBYug1WfKg2pxWG7w4ycjtAjfG0f/BF7 Pmnu6Kx2OWMs5RrZ3isa1/EgEEkGTkLUFgGdVyHug0gBguWE04dlbuJjz4iagasTeYAF eFjeRp4gKoT4Q00jodm9pXnupe1dGHav4ktVZ1BztcUSAo/N1J0J8nmsizxfEIQ7zobJ 7F1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680826449; h=content-transfer-encoding:to:from:subject:references:mime-version :message-id:in-reply-to:date:x-gm-message-state:from:to:cc:subject :date:message-id:reply-to; bh=KeEmcDWFc/SldpK/ezWRwN2cNjE5XRErQ4PS7868Kmc=; b=UjPNN2Bh6yS8HzcZYKqjHeZHC17ofyLGkp+CLfsirq6/cxC4kZ3gLRs6SvasTZNJn8 CZrwbXT9paXCUEN2jJ+PYEpDsVRiSdUgAfGNxqZyeDl3VyE2dT8mYhXEtOHDDZE5oDM6 lpB/x5vwVsxb73QLbd8CAMlfFh3GmDV+0MwGVLI1IErJ14vmvTrZoKR0uAjLDRinhhry 0exIGPdk1yChK4XGizA9E3MQwv+1ax8CFCeWzeQXx664Va9CQTAl82agczHBvu6B1jbB yKfxW4OwkaYc5mfxehcNMJ5bdGUW+k1pOc+jwBGU8xH2im3WdrDMHujAHP6DkEHmkiSg SCtQ== X-Gm-Message-State: AAQBX9eePNNsTsYo9TlLZhSPNa71z7U8c7556d7EOi8clig7NjhEzhfV dWMMYT7z6l3NIrDHZX/sdam8PjftzG1e X-Google-Smtp-Source: AKy350Z5iVwBurGhTZMdJuwOmKg8pCaiq+cNtDRoXzXdHs5HtY4QaYbPF85Qs31OVZAxs57l4Bh8fhGt4Esc X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:939d:185a:97bb:59ee]) (user=irogers job=sendgmr) by 2002:a25:734d:0:b0:b76:3b21:b1dc with SMTP id o74-20020a25734d000000b00b763b21b1dcmr228053ybc.0.1680826449608; Thu, 06 Apr 2023 17:14:09 -0700 (PDT) Date: Thu, 6 Apr 2023 17:13:22 -0700 In-Reply-To: <20230407001322.2776268-1-irogers@google.com> Message-Id: <20230407001322.2776268-5-irogers@google.com> Mime-Version: 1.0 References: <20230407001322.2776268-1-irogers@google.com> X-Mailer: git-send-email 2.40.0.577.gac1e443424-goog Subject: [PATCH v2 5/5] perf vendor events intel: Update free running tigerlake events From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Ian Rogers , Adrian Hunter , Kan Liang , Zhengjun Xing , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-perf-users@vger.kernel.org Fix the topic, PMU name, event code and umask. These updates were generated by: https://github.com/intel/perfmon/blob/main/scripts/create_perf_json.py with this PR: https://github.com/intel/perfmon/pull/66 Signed-off-by: Ian Rogers --- .../arch/x86/tigerlake/uncore-memory.json | 50 +++++++++++++++++++ .../arch/x86/tigerlake/uncore-other.json | 36 ------------- 2 files changed, 50 insertions(+), 36 deletions(-) create mode 100644 tools/perf/pmu-events/arch/x86/tigerlake/uncore-memory.= json diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/uncore-memory.json b/= tools/perf/pmu-events/arch/x86/tigerlake/uncore-memory.json new file mode 100644 index 000000000000..99fb5259fd25 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/tigerlake/uncore-memory.json @@ -0,0 +1,50 @@ +[ + { + "BriefDescription": "Counts every read (RdCAS) issued by the Memor= y Controller to DRAM (sum of all channels). All requests result in 64 byte = data transfers from DRAM.", + "EventCode": "0xff", + "EventName": "UNC_MC0_RDCAS_COUNT_FREERUN", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "imc_free_running_0" + }, + { + "BriefDescription": "Counts every 64B read and write request enter= ing the Memory Controller to DRAM (sum of all channels). Each write request= counts as a new request incrementing this counter. However, same cache lin= e write requests (both full and partial) are combined to a single 64 byte d= ata transfer to DRAM.", + "EventCode": "0xff", + "EventName": "UNC_MC0_TOTAL_REQCOUNT_FREERUN", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "imc_free_running_0" + }, + { + "BriefDescription": "Counts every write (WrCAS) issued by the Memo= ry Controller to DRAM (sum of all channels). All requests result in 64 byte= data transfers from DRAM.", + "EventCode": "0xff", + "EventName": "UNC_MC0_WRCAS_COUNT_FREERUN", + "PerPkg": "1", + "UMask": "0x30", + "Unit": "imc_free_running_0" + }, + { + "BriefDescription": "Counts every read (RdCAS) issued by the Memor= y Controller to DRAM (sum of all channels). All requests result in 64 byte = data transfers from DRAM.", + "EventCode": "0xff", + "EventName": "UNC_MC1_RDCAS_COUNT_FREERUN", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "imc_free_running_1" + }, + { + "BriefDescription": "Counts every 64B read and write request enter= ing the Memory Controller to DRAM (sum of all channels). Each write request= counts as a new request incrementing this counter. However, same cache lin= e write requests (both full and partial) are combined to a single 64 byte d= ata transfer to DRAM.", + "EventCode": "0xff", + "EventName": "UNC_MC1_TOTAL_REQCOUNT_FREERUN", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "imc_free_running_1" + }, + { + "BriefDescription": "Counts every write (WrCAS) issued by the Memo= ry Controller to DRAM (sum of all channels). All requests result in 64 byte= data transfers from DRAM.", + "EventCode": "0xff", + "EventName": "UNC_MC1_WRCAS_COUNT_FREERUN", + "PerPkg": "1", + "UMask": "0x30", + "Unit": "imc_free_running_1" + } +] diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/uncore-other.json b/t= ools/perf/pmu-events/arch/x86/tigerlake/uncore-other.json index a5a254327ae9..6e43aaf64e28 100644 --- a/tools/perf/pmu-events/arch/x86/tigerlake/uncore-other.json +++ b/tools/perf/pmu-events/arch/x86/tigerlake/uncore-other.json @@ -93,41 +93,5 @@ "EventName": "UNC_CLOCK.SOCKET", "PerPkg": "1", "Unit": "CLOCK" - }, - { - "BriefDescription": "Counts every read (RdCAS) issued by the Memor= y Controller to DRAM (sum of all channels). All requests result in 64 byte = data transfers from DRAM.", - "EventName": "UNC_MC0_RDCAS_COUNT_FREERUN", - "PerPkg": "1", - "Unit": "imc" - }, - { - "BriefDescription": "Counts every 64B read and write request enter= ing the Memory Controller to DRAM (sum of all channels). Each write request= counts as a new request incrementing this counter. However, same cache lin= e write requests (both full and partial) are combined to a single 64 byte d= ata transfer to DRAM.", - "EventName": "UNC_MC0_TOTAL_REQCOUNT_FREERUN", - "PerPkg": "1", - "Unit": "imc" - }, - { - "BriefDescription": "Counts every write (WrCAS) issued by the Memo= ry Controller to DRAM (sum of all channels). All requests result in 64 byte= data transfers from DRAM.", - "EventName": "UNC_MC0_WRCAS_COUNT_FREERUN", - "PerPkg": "1", - "Unit": "imc" - }, - { - "BriefDescription": "Counts every read (RdCAS) issued by the Memor= y Controller to DRAM (sum of all channels). All requests result in 64 byte = data transfers from DRAM.", - "EventName": "UNC_MC1_RDCAS_COUNT_FREERUN", - "PerPkg": "1", - "Unit": "imc" - }, - { - "BriefDescription": "Counts every 64B read and write request enter= ing the Memory Controller to DRAM (sum of all channels). Each write request= counts as a new request incrementing this counter. However, same cache lin= e write requests (both full and partial) are combined to a single 64 byte d= ata transfer to DRAM.", - "EventName": "UNC_MC1_TOTAL_REQCOUNT_FREERUN", - "PerPkg": "1", - "Unit": "imc" - }, - { - "BriefDescription": "Counts every write (WrCAS) issued by the Memo= ry Controller to DRAM (sum of all channels). All requests result in 64 byte= data transfers from DRAM.", - "EventName": "UNC_MC1_WRCAS_COUNT_FREERUN", - "PerPkg": "1", - "Unit": "imc" } ] --=20 2.40.0.577.gac1e443424-goog