From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 04BC8C77B60 for ; Sat, 29 Apr 2023 05:36:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347239AbjD2Fgq (ORCPT ); Sat, 29 Apr 2023 01:36:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38012 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230219AbjD2Fgg (ORCPT ); Sat, 29 Apr 2023 01:36:36 -0400 Received: from mail-yb1-xb49.google.com (mail-yb1-xb49.google.com [IPv6:2607:f8b0:4864:20::b49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A24E03C33 for ; Fri, 28 Apr 2023 22:36:07 -0700 (PDT) Received: by mail-yb1-xb49.google.com with SMTP id 3f1490d57ef6-b9a7e76b32bso614091276.1 for ; Fri, 28 Apr 2023 22:36:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1682746567; x=1685338567; h=content-transfer-encoding:cc:to:from:subject:references :mime-version:message-id:in-reply-to:date:from:to:cc:subject:date :message-id:reply-to; bh=pu+qnvO2EIt8egj2Q0XgeZXFcabh0X5taGysX92E8Pc=; b=4FB1e9s+iifNzXkJyEoJpEvX4pIR0C7GC7eaDlHiZXklTlNkjAwxLo+Dft9f7flsmW kcqhzUwUy9ehqzQMYKHRygRbEvFzmBhERVYeDrCOaMkwVjRKg46j3NNSIwAnOJLhOeH3 mPcHacAgWYxMSc7/KrtCGHmwl87fym47TuMknKNHJXSi+uVNiZPXezqCpzgyERY/BFSQ dYselZkk7TgLqoCzPZH0wFK2DsfjUMJ49uQ+K+VtX+tM2yW9tZLEOhIz42Ef5KWudLOl 4ls8QMe3HhtWDVCSjyauxH+9iWp5548ldfYBmBcdpUuHxGwZ2SssIRh7kdJ+x9QABPS+ nkqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682746567; x=1685338567; h=content-transfer-encoding:cc:to:from:subject:references :mime-version:message-id:in-reply-to:date:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=pu+qnvO2EIt8egj2Q0XgeZXFcabh0X5taGysX92E8Pc=; b=klB8GeEC0mydNpuouZQw39OtZzanzxzXZqm2bGeH9W1rXj8f040X6tu0wQNvR95HeN iSxTr+v5VF4VTyB7g/xmL4dBbcpW7LOe0QAHuyOET49xTNL+r7WvmVZe0a2jA33XUGpG F1Ob/LwEcJzXpwNPjTv56s98lCE0KIL+QepPE9HxzJIVqNDYdbDVzFOMWZfP5naleKkw oa79k3Fzp6lbCiEw5YF6ERe0RwwLDpgdX/hqdMwgCg63ZbvKKtADW8hxz1vPSaaOajhH 6cADycIvv17TGR5n8hwsTzO1hnqM5Wmf9xo/Cc53IVtVpJyukPknTe0RTWqyeB1GwHAD 7IDw== X-Gm-Message-State: AC+VfDypEq5YjJyhnJKvBmVzxp2z2WFve5+CdphEsHw8f0GVyOvcRLUE GV2S/0d05A8f7ucbEYZ01ZOiXut+wrPO X-Google-Smtp-Source: ACHHUZ5zIZVLrlwFePCR/MJseGZbrsS56nOWpJ4xW90I5R1CHnmXK3Hx88A+KBbBWJTHCFZjpvimwWvVn33B X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:c563:7e28:fb7c:bce3]) (user=irogers job=sendgmr) by 2002:a25:1fc6:0:b0:b8f:32c4:5cc4 with SMTP id f189-20020a251fc6000000b00b8f32c45cc4mr4485086ybf.4.1682746567350; Fri, 28 Apr 2023 22:36:07 -0700 (PDT) Date: Fri, 28 Apr 2023 22:34:26 -0700 In-Reply-To: <20230429053506.1962559-1-irogers@google.com> Message-Id: <20230429053506.1962559-7-irogers@google.com> Mime-Version: 1.0 References: <20230429053506.1962559-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v3 06/46] perf vendor events intel: Add alderlake metric constraints From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-perf-users@vger.kernel.org Previously these constraints were disabled as they contained topdown events. Since: https://lore.kernel.org/all/20230312021543.3060328-9-irogers@google.com/ the topdown events are correctly grouped even if no group exists. This change was created by PR: https://github.com/intel/perfmon/pull/71 Signed-off-by: Ian Rogers --- .../pmu-events/arch/x86/alderlake/adl-metrics.json | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/tools/perf/pmu-events/arch/x86/alderlake/adl-metrics.json b/to= ols/perf/pmu-events/arch/x86/alderlake/adl-metrics.json index 1f9047553942..4c2a14ea5a1c 100644 --- a/tools/perf/pmu-events/arch/x86/alderlake/adl-metrics.json +++ b/tools/perf/pmu-events/arch/x86/alderlake/adl-metrics.json @@ -1077,6 +1077,7 @@ }, { "BriefDescription": "This metric represents overall arithmetic flo= ating-point (FP) operations fraction the CPU has executed (retired)", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "tma_x87_use + tma_fp_scalar + tma_fp_vector", "MetricGroup": "HPC;TopdownL3;tma_L3_group;tma_light_operations_gr= oup", "MetricName": "tma_fp_arith", @@ -1203,6 +1204,7 @@ }, { "BriefDescription": "Branch Misprediction Cost: Fraction of TMA sl= ots wasted per non-speculative branch misprediction (retired JEClear)", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "(tma_branch_mispredicts + tma_fetch_latency * tma_m= ispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_= misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * tma_info_slots / B= R_MISP_RETIRED.ALL_BRANCHES", "MetricGroup": "Bad;BrMispredicts;tma_issueBM", "MetricName": "tma_info_branch_misprediction_cost", @@ -1255,6 +1257,7 @@ }, { "BriefDescription": "Probability of Core Bound bottleneck hidden b= y SMT-profiling artifacts", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "(100 * (1 - tma_core_bound / tma_ports_utilization = if tma_core_bound < tma_ports_utilization else 1) if tma_info_smt_2t_utiliz= ation > 0.5 else 0)", "MetricGroup": "Cor;SMT", "MetricName": "tma_info_core_bound_likely", @@ -1315,6 +1318,7 @@ }, { "BriefDescription": "Total pipeline cost of DSB (uop cache) misses= - subset of the Instruction_Fetch_BW Bottleneck", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * (tma_fetch_latency * tma_dsb_switches / (tma_= branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + = tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_mite / (tma_dsb + tm= a_lsd + tma_mite))", "MetricGroup": "DSBmiss;Fed;tma_issueFB", "MetricName": "tma_info_dsb_misses", @@ -1408,6 +1412,7 @@ }, { "BriefDescription": "Total pipeline cost of instruction fetch band= width related bottlenecks", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * (tma_frontend_bound - tma_fetch_latency * tma= _mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icach= e_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) - tma_info_big_cod= e", "MetricGroup": "Fed;FetchBW;Frontend", "MetricName": "tma_info_instruction_fetch_bw", @@ -1827,6 +1832,7 @@ }, { "BriefDescription": "Total pipeline cost of Memory Address Transla= tion related bottlenecks (data-side TLBs)", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * tma_memory_bound * (tma_l1_bound / max(tma_me= mory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + t= ma_store_bound) * (tma_dtlb_load / max(tma_l1_bound, tma_dtlb_load + tma_fb= _full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_stor= e_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tm= a_store_bound) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tm= a_split_stores + tma_store_latency + tma_streaming_stores)))", "MetricGroup": "Mem;MemoryTLB;Offcore;tma_issueTLB", "MetricName": "tma_info_memory_data_tlbs", @@ -1836,6 +1842,7 @@ }, { "BriefDescription": "Total pipeline cost of Memory Latency related= bottlenecks (external memory and off-core caches)", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dra= m_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (= tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (= tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bou= nd) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tm= a_l3_hit_latency + tma_sq_full)) + tma_l2_bound / (tma_dram_bound + tma_l1_= bound + tma_l2_bound + tma_l3_bound + tma_store_bound))", "MetricGroup": "Mem;MemoryLat;Offcore;tma_issueLat", "MetricName": "tma_info_memory_latency", @@ -1845,6 +1852,7 @@ }, { "BriefDescription": "Total pipeline cost of Branch Misprediction r= elated bottlenecks", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * (tma_branch_mispredicts + tma_fetch_latency *= tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_i= cache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))", "MetricGroup": "Bad;BadSpec;BrMispredicts;tma_issueBM", "MetricName": "tma_info_mispredictions", @@ -1877,6 +1885,7 @@ }, { "BriefDescription": "Average number of Uops retired in cycles wher= e at least one uop has retired.", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "tma_retiring * tma_info_slots / cpu_core@UOPS_RETIR= ED.SLOTS\\,cmask\\=3D1@", "MetricGroup": "Pipeline;Ret", "MetricName": "tma_info_retire", @@ -2152,6 +2161,7 @@ }, { "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring memory operations -- uops for memory load or store a= ccesses.", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "tma_light_operations * MEM_UOP_RETIRED.ANY / (tma_r= etiring * tma_info_slots)", "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operatio= ns_group", "MetricName": "tma_memory_operations", @@ -2231,6 +2241,7 @@ }, { "BriefDescription": "This metric represents the remaining light uo= ps fraction the CPU has executed - remaining means not covered by other sib= ling nodes", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "max(0, tma_light_operations - (tma_fp_arith + tma_i= nt_operations + tma_memory_operations + tma_fused_instructions + tma_non_fu= sed_branches + tma_nop_instructions))", "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operatio= ns_group", "MetricName": "tma_other_light_ops", --=20 2.40.1.495.gc816e09b53d-goog