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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT076.mail.protection.outlook.com (10.13.173.204) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6363.26 via Frontend Transport; Thu, 4 May 2023 11:01:23 +0000 Received: from BLR-5CG113396H.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Thu, 4 May 2023 06:00:18 -0500 From: Ravi Bangoria To: CC: , , , , , , , , , , , , , , , , Subject: [PATCH v4 0/4] perf: Rework event forwarding logic Date: Thu, 4 May 2023 16:29:59 +0530 Message-ID: <20230504110003.2548-1-ravi.bangoria@amd.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT076:EE_|SA1PR12MB6917:EE_ X-MS-Office365-Filtering-Correlation-Id: f36c6e9c-549f-43d4-1fc1-08db4c8ee687 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 May 2023 11:01:23.8801 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f36c6e9c-549f-43d4-1fc1-08db4c8ee687 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT076.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB6917 Precedence: bulk List-ID: X-Mailing-List: linux-perf-users@vger.kernel.org Usually, events are opened on the same pmu as requested by user via perf_event_attr->type argument. But certain special events are internally redirected to different pmu. Currently such pmus needs to be treated specially and thus requires some gruesome hacks. An approach, suggested by Peter Zijlstra, to get rid of these hacks was to overwrite event attributes with new pmu's attribute values within the kernel and let perf_event_init() retry opening the event with overwritten values. This patch series implements it. v3: https://lore.kernel.org/r/20230425142205.762-1-ravi.bangoria@amd.com v3->v4: - Split pmu linear searching changes into a separate patch with few additional changes. - Use special pointer value (void *)(~0) instead of introducing new variable to skip creating sysfs/dev files. - Move AMD IBS unit test under tools/perf/arch/x86/tests/ Patches are prepared on v6.3. Ravi Bangoria (4): perf/core: Rework forwarding of {task|cpu}-clock events perf/ibs: Fix interface via core pmu events perf/core: Remove pmu linear searching code perf test: Add selftest to test IBS invocation via core pmu events arch/x86/events/amd/core.c | 2 +- arch/x86/events/amd/ibs.c | 53 ++++---- arch/x86/include/asm/perf_event.h | 2 + include/linux/perf_event.h | 10 ++ kernel/events/core.c | 114 +++++++++--------- tools/perf/arch/x86/include/arch-tests.h | 1 + tools/perf/arch/x86/tests/Build | 1 + .../arch/x86/tests/amd-ibs-via-core-pmu.c | 71 +++++++++++ tools/perf/arch/x86/tests/arch-tests.c | 2 + 9 files changed, 168 insertions(+), 88 deletions(-) create mode 100644 tools/perf/arch/x86/tests/amd-ibs-via-core-pmu.c -- 2.40.0