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[92.145.124.62]) by smtp.gmail.com with ESMTPSA id f26-20020a7bcd1a000000b003f423f5b659sm15364363wmj.10.2023.05.12.02.02.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 May 2023 02:02:02 -0700 (PDT) From: Alexandre Ghiti To: Jonathan Corbet , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Ian Rogers , Paul Walmsley , Palmer Dabbelt , Albert Ou , Atish Patra , Anup Patel , Will Deacon , Rob Herring , Andrew Jones , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org Cc: Alexandre Ghiti Subject: [PATCH v2 08/10] Documentation: admin-guide: Add riscv sysctl_perf_user_access Date: Fri, 12 May 2023 10:53:19 +0200 Message-Id: <20230512085321.13259-9-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230512085321.13259-1-alexghiti@rivosinc.com> References: <20230512085321.13259-1-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-perf-users@vger.kernel.org riscv now uses this sysctl so document its usage for this architecture. Signed-off-by: Alexandre Ghiti --- Documentation/admin-guide/sysctl/kernel.rst | 24 +++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/Documentation/admin-guide/sysctl/kernel.rst b/Documentation/admin-guide/sysctl/kernel.rst index 4b7bfea28cd7..93cd518ca94b 100644 --- a/Documentation/admin-guide/sysctl/kernel.rst +++ b/Documentation/admin-guide/sysctl/kernel.rst @@ -941,16 +941,32 @@ enabled, otherwise writing to this file will return ``-EBUSY``. The default value is 8. -perf_user_access (arm64 only) -================================= +perf_user_access (arm64 and riscv only) +======================================= + +Controls user space access for reading perf event counters. -Controls user space access for reading perf event counters. When set to 1, -user space can read performance monitor counter registers directly. +arm64 +===== The default value is 0 (access disabled). +When set to 1, user space can read performance monitor counter registers +directly. See Documentation/arm64/perf.rst for more information. +riscv +===== + +When set to 0, user access is disabled. + +When set to 1, user space can read performance monitor counter registers +directly only through perf, any direct access without perf intervention will +trigger an illegal instruction. + +The default value is 2, which enables legacy mode (user space has direct +access to cycle, time and insret CSRs only). Note that this legacy value +is deprecated and will be removed once all userspace applications are fixed. pid_max ======= -- 2.37.2