From: Andrew Jones <ajones@ventanamicro.com>
To: Alexandre Ghiti <alexghiti@rivosinc.com>
Cc: Jonathan Corbet <corbet@lwn.net>,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Jiri Olsa <jolsa@kernel.org>, Namhyung Kim <namhyung@kernel.org>,
Ian Rogers <irogers@google.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Atish Patra <atishp@atishpatra.org>,
Anup Patel <anup@brainfault.org>, Will Deacon <will@kernel.org>,
Rob Herring <robh@kernel.org>,
linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-perf-users@vger.kernel.org,
linux-riscv@lists.infradead.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2 06/10] drivers: perf: Implement perf event mmap support in the legacy backend
Date: Wed, 31 May 2023 16:27:38 +0200 [thread overview]
Message-ID: <20230531-705f2911e8d66938ece04905@orel> (raw)
In-Reply-To: <20230512085321.13259-7-alexghiti@rivosinc.com>
On Fri, May 12, 2023 at 10:53:17AM +0200, Alexandre Ghiti wrote:
> Implement the needed callbacks in the legacy driver so that we can
> directly access the counters through perf in userspace.
>
> Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
> ---
> drivers/perf/riscv_pmu_legacy.c | 28 ++++++++++++++++++++++++++++
> 1 file changed, 28 insertions(+)
>
> diff --git a/drivers/perf/riscv_pmu_legacy.c b/drivers/perf/riscv_pmu_legacy.c
> index ffe09d857366..f0f5bd856f66 100644
> --- a/drivers/perf/riscv_pmu_legacy.c
> +++ b/drivers/perf/riscv_pmu_legacy.c
> @@ -74,6 +74,31 @@ static void pmu_legacy_ctr_start(struct perf_event *event, u64 ival)
> local64_set(&hwc->prev_count, initial_val);
> }
>
> +static uint8_t pmu_legacy_csr_index(struct perf_event *event)
> +{
> + return event->hw.idx;
> +}
> +
> +static void pmu_legacy_event_mapped(struct perf_event *event, struct mm_struct *mm)
> +{
> + /* In legacy mode, the first 3 CSRs are available. */
Shouldn't this be
/* In legacy mode, the first and third CSR are available. */
?
> + if (event->attr.config != PERF_COUNT_HW_CPU_CYCLES &&
> + event->attr.config != PERF_COUNT_HW_INSTRUCTIONS)
> + return;
> +
> + event->hw.flags |= PERF_EVENT_FLAG_USER_READ_CNT;
> +}
> +
> +static void pmu_legacy_event_unmapped(struct perf_event *event, struct mm_struct *mm)
> +{
> + /* In legacy mode, the first 3 CSRs are available. */
same comment
> + if (event->attr.config != PERF_COUNT_HW_CPU_CYCLES &&
> + event->attr.config != PERF_COUNT_HW_INSTRUCTIONS)
> + return;
> +
> + event->hw.flags &= ~PERF_EVENT_FLAG_USER_READ_CNT;
> +}
> +
> /*
> * This is just a simple implementation to allow legacy implementations
> * compatible with new RISC-V PMU driver framework.
> @@ -94,6 +119,9 @@ static void pmu_legacy_init(struct riscv_pmu *pmu)
> pmu->ctr_get_width = NULL;
> pmu->ctr_clear_idx = NULL;
> pmu->ctr_read = pmu_legacy_read_ctr;
> + pmu->event_mapped = pmu_legacy_event_mapped;
> + pmu->event_unmapped = pmu_legacy_event_unmapped;
> + pmu->csr_index = pmu_legacy_csr_index;
>
> perf_pmu_register(&pmu->pmu, RISCV_PMU_LEGACY_PDEV_NAME, PERF_TYPE_RAW);
> }
> --
> 2.37.2
>
Otherwise,
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
next prev parent reply other threads:[~2023-05-31 14:27 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-12 8:53 [PATCH v2 00/10] riscv: Allow userspace to directly access perf counters Alexandre Ghiti
2023-05-12 8:53 ` [PATCH v2 01/10] perf: Fix wrong comment about default event_idx Alexandre Ghiti
2023-05-31 13:54 ` Andrew Jones
2023-06-15 7:10 ` Alexandre Ghiti
2023-06-15 8:24 ` Atish Patra
2023-05-12 8:53 ` [PATCH v2 02/10] include: riscv: Fix wrong include guard in riscv_pmu.h Alexandre Ghiti
2023-05-31 13:56 ` Andrew Jones
2023-06-15 8:36 ` Atish Patra
2023-05-12 8:53 ` [PATCH v2 03/10] riscv: Make legacy counter enum match the HW numbering Alexandre Ghiti
2023-05-31 14:01 ` Andrew Jones
2023-06-15 7:16 ` Alexandre Ghiti
2023-05-12 8:53 ` [PATCH v2 04/10] drivers: perf: Rename riscv pmu driver Alexandre Ghiti
2023-05-31 14:09 ` Andrew Jones
2023-06-15 7:25 ` Alexandre Ghiti
2023-06-15 8:34 ` Atish Patra
2023-05-12 8:53 ` [PATCH v2 05/10] riscv: Prepare for user-space perf event mmap support Alexandre Ghiti
2023-05-31 14:24 ` Andrew Jones
2023-06-16 8:28 ` Atish Patra
2023-06-16 8:56 ` Alexandre Ghiti
2023-06-20 15:27 ` Atish Patra
2023-05-12 8:53 ` [PATCH v2 06/10] drivers: perf: Implement perf event mmap support in the legacy backend Alexandre Ghiti
2023-05-31 14:27 ` Andrew Jones [this message]
2023-06-15 7:38 ` Alexandre Ghiti
2023-05-12 8:53 ` [PATCH v2 07/10] drivers: perf: Implement perf event mmap support in the SBI backend Alexandre Ghiti
2023-05-31 15:02 ` Andrew Jones
2023-06-15 8:41 ` Atish Patra
2023-06-15 13:27 ` Heinrich Schuchardt
2023-06-16 7:44 ` Atish Patra
2023-06-15 9:52 ` Alexandre Ghiti
2023-05-12 8:53 ` [PATCH v2 08/10] Documentation: admin-guide: Add riscv sysctl_perf_user_access Alexandre Ghiti
2023-05-31 15:07 ` Andrew Jones
2023-05-31 17:08 ` Atish Patra
2023-06-15 10:00 ` Alexandre Ghiti
2023-05-12 8:53 ` [PATCH v2 09/10] tools: lib: perf: Implement riscv mmap support Alexandre Ghiti
2023-05-31 15:12 ` Andrew Jones
2023-06-16 8:43 ` Atish Patra
2023-06-16 9:06 ` Alexandre Ghiti
2023-06-19 19:04 ` Atish Patra
2023-05-12 8:53 ` [PATCH v2 10/10] perf: tests: Adapt mmap-basic.c for riscv Alexandre Ghiti
2023-05-31 15:15 ` Andrew Jones
2023-06-05 13:53 ` Arnaldo Carvalho de Melo
2023-06-05 14:02 ` Alexandre Ghiti
[not found] ` <CAHVXubhofC+WaSysWaxcTA2GdJAF8kTD3COBeQDAy25af_rSLg@mail.gmail.com>
2023-06-05 14:31 ` Arnaldo Carvalho de Melo
2023-06-15 10:02 ` Alexandre Ghiti
2023-05-15 17:50 ` [PATCH v2 00/10] riscv: Allow userspace to directly access perf counters Conor Dooley
2023-06-21 23:37 ` Palmer Dabbelt
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