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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id l4-20020a05600012c400b003047dc162f7sm7057593wrx.67.2023.05.31.07.27.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 May 2023 07:27:39 -0700 (PDT) Date: Wed, 31 May 2023 16:27:38 +0200 From: Andrew Jones To: Alexandre Ghiti Cc: Jonathan Corbet , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Ian Rogers , Paul Walmsley , Palmer Dabbelt , Albert Ou , Atish Patra , Anup Patel , Will Deacon , Rob Herring , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v2 06/10] drivers: perf: Implement perf event mmap support in the legacy backend Message-ID: <20230531-705f2911e8d66938ece04905@orel> References: <20230512085321.13259-1-alexghiti@rivosinc.com> <20230512085321.13259-7-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230512085321.13259-7-alexghiti@rivosinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-perf-users@vger.kernel.org On Fri, May 12, 2023 at 10:53:17AM +0200, Alexandre Ghiti wrote: > Implement the needed callbacks in the legacy driver so that we can > directly access the counters through perf in userspace. > > Signed-off-by: Alexandre Ghiti > --- > drivers/perf/riscv_pmu_legacy.c | 28 ++++++++++++++++++++++++++++ > 1 file changed, 28 insertions(+) > > diff --git a/drivers/perf/riscv_pmu_legacy.c b/drivers/perf/riscv_pmu_legacy.c > index ffe09d857366..f0f5bd856f66 100644 > --- a/drivers/perf/riscv_pmu_legacy.c > +++ b/drivers/perf/riscv_pmu_legacy.c > @@ -74,6 +74,31 @@ static void pmu_legacy_ctr_start(struct perf_event *event, u64 ival) > local64_set(&hwc->prev_count, initial_val); > } > > +static uint8_t pmu_legacy_csr_index(struct perf_event *event) > +{ > + return event->hw.idx; > +} > + > +static void pmu_legacy_event_mapped(struct perf_event *event, struct mm_struct *mm) > +{ > + /* In legacy mode, the first 3 CSRs are available. */ Shouldn't this be /* In legacy mode, the first and third CSR are available. */ ? > + if (event->attr.config != PERF_COUNT_HW_CPU_CYCLES && > + event->attr.config != PERF_COUNT_HW_INSTRUCTIONS) > + return; > + > + event->hw.flags |= PERF_EVENT_FLAG_USER_READ_CNT; > +} > + > +static void pmu_legacy_event_unmapped(struct perf_event *event, struct mm_struct *mm) > +{ > + /* In legacy mode, the first 3 CSRs are available. */ same comment > + if (event->attr.config != PERF_COUNT_HW_CPU_CYCLES && > + event->attr.config != PERF_COUNT_HW_INSTRUCTIONS) > + return; > + > + event->hw.flags &= ~PERF_EVENT_FLAG_USER_READ_CNT; > +} > + > /* > * This is just a simple implementation to allow legacy implementations > * compatible with new RISC-V PMU driver framework. > @@ -94,6 +119,9 @@ static void pmu_legacy_init(struct riscv_pmu *pmu) > pmu->ctr_get_width = NULL; > pmu->ctr_clear_idx = NULL; > pmu->ctr_read = pmu_legacy_read_ctr; > + pmu->event_mapped = pmu_legacy_event_mapped; > + pmu->event_unmapped = pmu_legacy_event_unmapped; > + pmu->csr_index = pmu_legacy_csr_index; > > perf_pmu_register(&pmu->pmu, RISCV_PMU_LEGACY_PDEV_NAME, PERF_TYPE_RAW); > } > -- > 2.37.2 > Otherwise, Reviewed-by: Andrew Jones