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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id va15-20020a17090711cf00b0094ee99eeb01sm9041514ejb.150.2023.05.31.06.56.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 May 2023 06:56:10 -0700 (PDT) Date: Wed, 31 May 2023 15:56:10 +0200 From: Andrew Jones To: Alexandre Ghiti Cc: Jonathan Corbet , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Ian Rogers , Paul Walmsley , Palmer Dabbelt , Albert Ou , Atish Patra , Anup Patel , Will Deacon , Rob Herring , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Conor Dooley Subject: Re: [PATCH v2 02/10] include: riscv: Fix wrong include guard in riscv_pmu.h Message-ID: <20230531-707d254be1238272fb2c182d@orel> References: <20230512085321.13259-1-alexghiti@rivosinc.com> <20230512085321.13259-3-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230512085321.13259-3-alexghiti@rivosinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-perf-users@vger.kernel.org On Fri, May 12, 2023 at 10:53:13AM +0200, Alexandre Ghiti wrote: > The current include guard prevents the inclusion of asm/perf_event.h > which uses the same include guard: fix the one in riscv_pmu.h so that it > matches the file name. > > Signed-off-by: Alexandre Ghiti > Reviewed-by: Conor Dooley > --- > include/linux/perf/riscv_pmu.h | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/include/linux/perf/riscv_pmu.h b/include/linux/perf/riscv_pmu.h > index 43fc892aa7d9..9f70d94942e0 100644 > --- a/include/linux/perf/riscv_pmu.h > +++ b/include/linux/perf/riscv_pmu.h > @@ -6,8 +6,8 @@ > * > */ > > -#ifndef _ASM_RISCV_PERF_EVENT_H > -#define _ASM_RISCV_PERF_EVENT_H > +#ifndef _RISCV_PMU_H > +#define _RISCV_PMU_H > > #include > #include > @@ -81,4 +81,4 @@ int riscv_pmu_get_hpm_info(u32 *hw_ctr_width, u32 *num_hw_ctr); > > #endif /* CONFIG_RISCV_PMU */ > > -#endif /* _ASM_RISCV_PERF_EVENT_H */ > +#endif /* _RISCV_PMU_H */ > -- > 2.37.2 > Reviewed-by: Andrew Jones