From: Andrew Jones <ajones@ventanamicro.com>
To: Alexandre Ghiti <alexghiti@rivosinc.com>
Cc: Jonathan Corbet <corbet@lwn.net>,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Jiri Olsa <jolsa@kernel.org>, Namhyung Kim <namhyung@kernel.org>,
Ian Rogers <irogers@google.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Atish Patra <atishp@atishpatra.org>,
Anup Patel <anup@brainfault.org>, Will Deacon <will@kernel.org>,
Rob Herring <robh@kernel.org>,
linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-perf-users@vger.kernel.org,
linux-riscv@lists.infradead.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v3 03/10] riscv: Make legacy counter enum match the HW numbering
Date: Fri, 30 Jun 2023 12:35:03 +0200 [thread overview]
Message-ID: <20230630-ba45f06f3d9faba17c6d8f6a@orel> (raw)
In-Reply-To: <20230630083013.102334-4-alexghiti@rivosinc.com>
On Fri, Jun 30, 2023 at 10:30:06AM +0200, Alexandre Ghiti wrote:
> RISCV_PMU_LEGACY_INSTRET used to be set to 1 whereas the offset of this
> hardware counter from CSR_CYCLE is actually 2: make this offset match the
> real hw offset so that we can directly expose those values to userspace.
>
> Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
> ---
> drivers/perf/riscv_pmu_legacy.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/perf/riscv_pmu_legacy.c b/drivers/perf/riscv_pmu_legacy.c
> index ca9e20bfc7ac..6a000abc28bb 100644
> --- a/drivers/perf/riscv_pmu_legacy.c
> +++ b/drivers/perf/riscv_pmu_legacy.c
> @@ -13,7 +13,7 @@
> #include <linux/platform_device.h>
>
> #define RISCV_PMU_LEGACY_CYCLE 0
> -#define RISCV_PMU_LEGACY_INSTRET 1
> +#define RISCV_PMU_LEGACY_INSTRET 2
>
> static bool pmu_init_done;
>
> --
> 2.39.2
>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
next prev parent reply other threads:[~2023-06-30 10:35 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-30 8:30 [PATCH v3 00/10] riscv: Allow userspace to directly access perf counters Alexandre Ghiti
2023-06-30 8:30 ` [PATCH v3 01/10] perf: Fix wrong comment about default event_idx Alexandre Ghiti
2023-06-30 8:30 ` [PATCH v3 02/10] include: riscv: Fix wrong include guard in riscv_pmu.h Alexandre Ghiti
2023-06-30 8:30 ` [PATCH v3 03/10] riscv: Make legacy counter enum match the HW numbering Alexandre Ghiti
2023-06-30 10:35 ` Andrew Jones [this message]
2023-06-30 8:30 ` [PATCH v3 04/10] drivers: perf: Rename riscv pmu sbi driver Alexandre Ghiti
2023-06-30 8:30 ` [PATCH v3 05/10] riscv: Prepare for user-space perf event mmap support Alexandre Ghiti
2023-06-30 8:30 ` [PATCH v3 06/10] drivers: perf: Implement perf event mmap support in the legacy backend Alexandre Ghiti
2023-06-30 8:30 ` [PATCH v3 07/10] drivers: perf: Implement perf event mmap support in the SBI backend Alexandre Ghiti
2023-06-30 11:08 ` Andrew Jones
2023-07-03 9:21 ` Alexandre Ghiti
2023-06-30 8:30 ` [PATCH v3 08/10] Documentation: admin-guide: Add riscv sysctl_perf_user_access Alexandre Ghiti
2023-06-30 11:16 ` Andrew Jones
2023-07-03 9:45 ` Alexandre Ghiti
2023-06-30 8:30 ` [PATCH v3 09/10] tools: lib: perf: Implement riscv mmap support Alexandre Ghiti
2023-06-30 8:30 ` [PATCH v3 10/10] perf: tests: Adapt mmap-basic.c for riscv Alexandre Ghiti
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