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From: Andrew Jones <ajones@ventanamicro.com>
To: Alexandre Ghiti <alexghiti@rivosinc.com>
Cc: Jonathan Corbet <corbet@lwn.net>,
	Peter Zijlstra <peterz@infradead.org>,
	Ingo Molnar <mingo@redhat.com>,
	Arnaldo Carvalho de Melo <acme@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Alexander Shishkin <alexander.shishkin@linux.intel.com>,
	Jiri Olsa <jolsa@kernel.org>, Namhyung Kim <namhyung@kernel.org>,
	Ian Rogers <irogers@google.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Atish Patra <atishp@atishpatra.org>,
	Anup Patel <anup@brainfault.org>, Will Deacon <will@kernel.org>,
	Rob Herring <robh@kernel.org>,
	linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-perf-users@vger.kernel.org,
	linux-riscv@lists.infradead.org,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v3 08/10] Documentation: admin-guide: Add riscv sysctl_perf_user_access
Date: Fri, 30 Jun 2023 13:16:41 +0200	[thread overview]
Message-ID: <20230630-f714cc46ee65cc65318f2ada@orel> (raw)
In-Reply-To: <20230630083013.102334-9-alexghiti@rivosinc.com>

On Fri, Jun 30, 2023 at 10:30:11AM +0200, Alexandre Ghiti wrote:
> riscv now uses this sysctl so document its usage for this architecture.
> 
> Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
> ---
>  Documentation/admin-guide/sysctl/kernel.rst | 26 +++++++++++++++++----
>  1 file changed, 22 insertions(+), 4 deletions(-)
> 
> diff --git a/Documentation/admin-guide/sysctl/kernel.rst b/Documentation/admin-guide/sysctl/kernel.rst
> index d85d90f5d000..c376692b372b 100644
> --- a/Documentation/admin-guide/sysctl/kernel.rst
> +++ b/Documentation/admin-guide/sysctl/kernel.rst
> @@ -941,16 +941,34 @@ enabled, otherwise writing to this file will return ``-EBUSY``.
>  The default value is 8.
>  
>  
> -perf_user_access (arm64 only)
> -=================================
> +perf_user_access (arm64 and riscv only)
> +=======================================
> +
> +Controls user space access for reading perf event counters.
>  
> -Controls user space access for reading perf event counters. When set to 1,
> -user space can read performance monitor counter registers directly.
> +arm64
> +=====
>  
>  The default value is 0 (access disabled).

Should add a blank line here.

> +When set to 1, user space can read performance monitor counter registers
> +directly.
>  
>  See Documentation/arm64/perf.rst for more information.
>  
> +riscv
> +=====
> +
> +When set to 0, user access is disabled.
> +
> +When set to 1, user space can read performance monitor counter registers
> +directly only through perf, any direct access without perf intervention will

Remove 'directly only'

(It can't be both "direct" and "through" at the same time.)

> +trigger an illegal instruction.
> +
> +The default value is 2,

This is no longer true.

> which enables legacy mode (user space has direct
> +access to cycle and insret CSRs only). Note that this legacy value
> +is deprecated and will be removed once all userspace applications are fixed.
> +
> +Note that the time CSR is for now always accessible to all modes.

s/always accessible/always directly accessible/

Also, remove 'for now'. While we may change this in the future, I'm not
sure if the 'for now' helps much. Maybe a "This may change in the future."
type of sentence? Or, just nothing (for now :-) and we'll modify this
document if it changes later.

Thanks,
drew

>  
>  pid_max
>  =======
> -- 
> 2.39.2
> 

  reply	other threads:[~2023-06-30 11:16 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-06-30  8:30 [PATCH v3 00/10] riscv: Allow userspace to directly access perf counters Alexandre Ghiti
2023-06-30  8:30 ` [PATCH v3 01/10] perf: Fix wrong comment about default event_idx Alexandre Ghiti
2023-06-30  8:30 ` [PATCH v3 02/10] include: riscv: Fix wrong include guard in riscv_pmu.h Alexandre Ghiti
2023-06-30  8:30 ` [PATCH v3 03/10] riscv: Make legacy counter enum match the HW numbering Alexandre Ghiti
2023-06-30 10:35   ` Andrew Jones
2023-06-30  8:30 ` [PATCH v3 04/10] drivers: perf: Rename riscv pmu sbi driver Alexandre Ghiti
2023-06-30  8:30 ` [PATCH v3 05/10] riscv: Prepare for user-space perf event mmap support Alexandre Ghiti
2023-06-30  8:30 ` [PATCH v3 06/10] drivers: perf: Implement perf event mmap support in the legacy backend Alexandre Ghiti
2023-06-30  8:30 ` [PATCH v3 07/10] drivers: perf: Implement perf event mmap support in the SBI backend Alexandre Ghiti
2023-06-30 11:08   ` Andrew Jones
2023-07-03  9:21     ` Alexandre Ghiti
2023-06-30  8:30 ` [PATCH v3 08/10] Documentation: admin-guide: Add riscv sysctl_perf_user_access Alexandre Ghiti
2023-06-30 11:16   ` Andrew Jones [this message]
2023-07-03  9:45     ` Alexandre Ghiti
2023-06-30  8:30 ` [PATCH v3 09/10] tools: lib: perf: Implement riscv mmap support Alexandre Ghiti
2023-06-30  8:30 ` [PATCH v3 10/10] perf: tests: Adapt mmap-basic.c for riscv Alexandre Ghiti

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