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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id u12-20020a1709064acc00b009930308425csm22356ejt.31.2023.06.30.04.16.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Jun 2023 04:16:42 -0700 (PDT) Date: Fri, 30 Jun 2023 13:16:41 +0200 From: Andrew Jones To: Alexandre Ghiti Cc: Jonathan Corbet , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Ian Rogers , Paul Walmsley , Palmer Dabbelt , Albert Ou , Atish Patra , Anup Patel , Will Deacon , Rob Herring , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v3 08/10] Documentation: admin-guide: Add riscv sysctl_perf_user_access Message-ID: <20230630-f714cc46ee65cc65318f2ada@orel> References: <20230630083013.102334-1-alexghiti@rivosinc.com> <20230630083013.102334-9-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230630083013.102334-9-alexghiti@rivosinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-perf-users@vger.kernel.org On Fri, Jun 30, 2023 at 10:30:11AM +0200, Alexandre Ghiti wrote: > riscv now uses this sysctl so document its usage for this architecture. > > Signed-off-by: Alexandre Ghiti > --- > Documentation/admin-guide/sysctl/kernel.rst | 26 +++++++++++++++++---- > 1 file changed, 22 insertions(+), 4 deletions(-) > > diff --git a/Documentation/admin-guide/sysctl/kernel.rst b/Documentation/admin-guide/sysctl/kernel.rst > index d85d90f5d000..c376692b372b 100644 > --- a/Documentation/admin-guide/sysctl/kernel.rst > +++ b/Documentation/admin-guide/sysctl/kernel.rst > @@ -941,16 +941,34 @@ enabled, otherwise writing to this file will return ``-EBUSY``. > The default value is 8. > > > -perf_user_access (arm64 only) > -================================= > +perf_user_access (arm64 and riscv only) > +======================================= > + > +Controls user space access for reading perf event counters. > > -Controls user space access for reading perf event counters. When set to 1, > -user space can read performance monitor counter registers directly. > +arm64 > +===== > > The default value is 0 (access disabled). Should add a blank line here. > +When set to 1, user space can read performance monitor counter registers > +directly. > > See Documentation/arm64/perf.rst for more information. > > +riscv > +===== > + > +When set to 0, user access is disabled. > + > +When set to 1, user space can read performance monitor counter registers > +directly only through perf, any direct access without perf intervention will Remove 'directly only' (It can't be both "direct" and "through" at the same time.) > +trigger an illegal instruction. > + > +The default value is 2, This is no longer true. > which enables legacy mode (user space has direct > +access to cycle and insret CSRs only). Note that this legacy value > +is deprecated and will be removed once all userspace applications are fixed. > + > +Note that the time CSR is for now always accessible to all modes. s/always accessible/always directly accessible/ Also, remove 'for now'. While we may change this in the future, I'm not sure if the 'for now' helps much. Maybe a "This may change in the future." type of sentence? Or, just nothing (for now :-) and we'll modify this document if it changes later. Thanks, drew > > pid_max > ======= > -- > 2.39.2 >