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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id d5-20020adff845000000b003141b9ddab3sm10587287wrq.114.2023.07.03.06.03.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Jul 2023 06:03:48 -0700 (PDT) Date: Mon, 3 Jul 2023 15:03:47 +0200 From: Andrew Jones To: Alexandre Ghiti Cc: Jonathan Corbet , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Ian Rogers , Paul Walmsley , Palmer Dabbelt , Albert Ou , Atish Patra , Anup Patel , Will Deacon , Rob Herring , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v4 08/10] Documentation: admin-guide: Add riscv sysctl_perf_user_access Message-ID: <20230703-c7f3e773f50ed6c934662f3f@orel> References: <20230703124647.215952-1-alexghiti@rivosinc.com> <20230703124647.215952-9-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230703124647.215952-9-alexghiti@rivosinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-perf-users@vger.kernel.org On Mon, Jul 03, 2023 at 02:46:45PM +0200, Alexandre Ghiti wrote: > riscv now uses this sysctl so document its usage for this architecture. > > Signed-off-by: Alexandre Ghiti > --- > Documentation/admin-guide/sysctl/kernel.rst | 27 ++++++++++++++++++--- > 1 file changed, 23 insertions(+), 4 deletions(-) > > diff --git a/Documentation/admin-guide/sysctl/kernel.rst b/Documentation/admin-guide/sysctl/kernel.rst > index d85d90f5d000..19b627883313 100644 > --- a/Documentation/admin-guide/sysctl/kernel.rst > +++ b/Documentation/admin-guide/sysctl/kernel.rst > @@ -941,16 +941,35 @@ enabled, otherwise writing to this file will return ``-EBUSY``. > The default value is 8. > > > -perf_user_access (arm64 only) > -================================= > +perf_user_access (arm64 and riscv only) > +======================================= > + > +Controls user space access for reading perf event counters. > > -Controls user space access for reading perf event counters. When set to 1, > -user space can read performance monitor counter registers directly. > +arm64 > +===== > > The default value is 0 (access disabled). > > +When set to 1, user space can read performance monitor counter registers > +directly. > + > See Documentation/arm64/perf.rst for more information. > > +riscv > +===== > + > +When set to 0, user space access is disabled. > + > +The default value is 1, user space can read performance monitor counter > +registers through perf, any direct access without perf intervention will trigger > +an illegal instruction. > + > +When set to 2, which enables legacy mode (user space has direct access to cycle > +and insret CSRs only). Note that this legacy value is deprecated and will be > +removed once all user space applications are fixed. > + > +Note that the time CSR is always directly accessible to all modes. > > pid_max > ======= > -- > 2.39.2 > Reviewed-by: Andrew Jones