From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1E4D9EB64DC for ; Mon, 17 Jul 2023 05:43:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231258AbjGQFnv (ORCPT ); Mon, 17 Jul 2023 01:43:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41344 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231278AbjGQFnr (ORCPT ); Mon, 17 Jul 2023 01:43:47 -0400 Received: from mail-qk1-x72b.google.com (mail-qk1-x72b.google.com [IPv6:2607:f8b0:4864:20::72b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CE71EE6E for ; Sun, 16 Jul 2023 22:43:38 -0700 (PDT) Received: by mail-qk1-x72b.google.com with SMTP id af79cd13be357-7672303c831so395193885a.2 for ; Sun, 16 Jul 2023 22:43:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1689572618; x=1692164618; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=uuuapjCm4uGRuklqDX8mlQes8ibPwf0zSHbcBhv1+wk=; b=YHIL+Q4b3CFfCYm9CihgC3tCGEJLGrMGXdGiZ2Bh6+7eKpxaMZRlVHfornWX0kWU7A crgNhpc+tHNK2BD7thw8Dqg2KDc41WFfz0xEmU9W6cWrMoeBgnyCDdJRfwoPsEmE5vOJ xcvrFigQLXZiyHn4D4MljNTGqQ7jZ/+Ms9EuulbqKhTTD6T0wixnoPGMZG9kfeMSDeXi felWXDFVueNqirjzjSV5jRmTc6FX0+6c9fRO2zfpXGJXVj+6EnwLyq4v0ROcrWb0Pr1R HlCNziFKcalhPrTXjhKkbLukviIh3aYFLpseQ9llEWD45v34k6O66ZZZVU1A+mp75msk 43dQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689572618; x=1692164618; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=uuuapjCm4uGRuklqDX8mlQes8ibPwf0zSHbcBhv1+wk=; b=e1AvJur8wCoXQB+WkXgAEDpV0MPdNMv9EZ8vbszhP7iRsUJuUIlE0isUK8+cc3snBR 5oXHGpeYFIMwtuZ9jQ3LUmvGmHNQ58KbLH9Gad9pT9CnWMjFwdXM7v8OYy2kUndq/6FV TZ2zYdDRwmGX1gy+Vd397+9oSm+T5QvdBLCunBZ1Swhpmo7BKicQJiSp3N2qAje0Y7ag TfDdXq78ojl/+DUKo4phHAlY9EkjVNkGDWhCpErSyeQWqxjQFimoWYExJc81NYfjgFOb HDuk9MC3NTLARKpylrKK4ujoSCuo30tmG1uq2tnTH6ClyBYE8jpImx35BjzyfxUL3Rga kS3Q== X-Gm-Message-State: ABy/qLaRMn0cocNTUJlBz0aRcyYwmcOKixwavH7r7r2pRQrLN4wkZc+5 HwNODYHLXwpgxm2AOMIYUjrd/w== X-Google-Smtp-Source: APBJJlFXTfi8g5jBhSbeBObDe11usDkfzwOunbCh7CEeZgDBWe4niHoSon7iQk0OGp5W9T40RiM4+w== X-Received: by 2002:a05:620a:4516:b0:765:a518:c31d with SMTP id t22-20020a05620a451600b00765a518c31dmr14358123qkp.54.1689572617873; Sun, 16 Jul 2023 22:43:37 -0700 (PDT) Received: from leoy-huanghe.lan (211-75-219-203.hinet-ip.hinet.net. [211.75.219.203]) by smtp.gmail.com with ESMTPSA id i14-20020a17090a2a0e00b00263e59c1a9fsm4625849pjd.34.2023.07.16.22.43.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Jul 2023 22:43:37 -0700 (PDT) From: Leo Yan To: Arnaldo Carvalho de Melo , Catalin Marinas , Will Deacon , John Garry , James Clark , Mike Leach , Peter Zijlstra , Ingo Molnar , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Ian Rogers , Adrian Hunter , D Scott Phillips , Marc Zyngier , Anshuman Khandual , German Gomez , Ali Saidi , Jing Zhang , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, fissure2010@gmail.com Cc: Leo Yan Subject: [PATCH v1 0/3] arm64: Support Cortex-X4 CPU for Perf Arm SPE Date: Mon, 17 Jul 2023 13:43:24 +0800 Message-Id: <20230717054327.79815-1-leo.yan@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-perf-users@vger.kernel.org This series support Cortex-X4 CPU in Perf Arm SPE. The Arm64 and tools both include the header cputype.h for CPU part and MIDR definitions, to de-couple between the tools and the kernel, the tools doesn't directly use the kernel's header, alternatively, the tools maintain a copy and sync with kernel's header. To keep the exact same content between kernel and tools' headers, this series firstly adds Cortex-X4 CPU part and MIDR definitions in the kernel header; then the second patch syncs the change into the tools' header. The first patch is to support the Cortex-X4 in perf Arm SPE with the new CPU definitions. I don't have Cortex-X4 machine in hand, so just verified with compilation perf tool. Leo Yan (3): arm64: Add Cortex-X4 CPU part definitions tools headers arm64: Sync Cortex-X4 CPU part definitions perf arm-spe: Support data source for Cortex-X4 CPU arch/arm64/include/asm/cputype.h | 2 ++ tools/arch/arm64/include/asm/cputype.h | 2 ++ tools/perf/util/arm-spe.c | 14 ++++++++------ 3 files changed, 12 insertions(+), 6 deletions(-) -- 2.34.1