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[211.75.219.203]) by smtp.gmail.com with ESMTPSA id i14-20020a17090a2a0e00b00263e59c1a9fsm4625849pjd.34.2023.07.16.22.43.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Jul 2023 22:43:56 -0700 (PDT) From: Leo Yan To: Arnaldo Carvalho de Melo , Catalin Marinas , Will Deacon , John Garry , James Clark , Mike Leach , Peter Zijlstra , Ingo Molnar , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Ian Rogers , Adrian Hunter , D Scott Phillips , Marc Zyngier , Anshuman Khandual , German Gomez , Ali Saidi , Jing Zhang , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, fissure2010@gmail.com Cc: Leo Yan Subject: [PATCH v1 3/3] perf arm-spe: Support data source for Cortex-X4 CPU Date: Mon, 17 Jul 2023 13:43:27 +0800 Message-Id: <20230717054327.79815-4-leo.yan@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230717054327.79815-1-leo.yan@linaro.org> References: <20230717054327.79815-1-leo.yan@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-perf-users@vger.kernel.org We have a CPU list to maintain Neoverse CPUs (N1/N2/V2), this list is used for parsing data source packet. Since Cortex-x4 CPU shares the same data source format with Neoverse CPUs, this commit adds Cortex-x4 CPU into the CPU list so we can reuse the parsing logic. The CPU list was assumed for only Neoverse CPUs, but now Cortex-X4 has been added into the list. To avoid Neoverse specific naming, this patch renames the variables and function as the default data source format. Signed-off-by: Leo Yan --- tools/perf/util/arm-spe.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c index afbd5869f6bf..c2cdb9f2e188 100644 --- a/tools/perf/util/arm-spe.c +++ b/tools/perf/util/arm-spe.c @@ -409,15 +409,16 @@ static int arm_spe__synth_instruction_sample(struct arm_spe_queue *speq, return arm_spe_deliver_synth_event(spe, speq, event, &sample); } -static const struct midr_range neoverse_spe[] = { +static const struct midr_range cpus_use_default_data_src[] = { MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1), MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1), + MIDR_ALL_VERSIONS(MIDR_CORTEX_X4), {}, }; -static void arm_spe__synth_data_source_neoverse(const struct arm_spe_record *record, - union perf_mem_data_src *data_src) +static void arm_spe__synth_data_source_default(const struct arm_spe_record *record, + union perf_mem_data_src *data_src) { /* * Even though four levels of cache hierarchy are possible, no known @@ -518,7 +519,8 @@ static void arm_spe__synth_data_source_generic(const struct arm_spe_record *reco static u64 arm_spe__synth_data_source(const struct arm_spe_record *record, u64 midr) { union perf_mem_data_src data_src = { .mem_op = PERF_MEM_OP_NA }; - bool is_neoverse = is_midr_in_range_list(midr, neoverse_spe); + bool is_default_dc = + is_midr_in_range_list(midr, cpus_use_default_data_src); if (record->op & ARM_SPE_OP_LD) data_src.mem_op = PERF_MEM_OP_LOAD; @@ -527,8 +529,8 @@ static u64 arm_spe__synth_data_source(const struct arm_spe_record *record, u64 m else return 0; - if (is_neoverse) - arm_spe__synth_data_source_neoverse(record, &data_src); + if (is_default_dc) + arm_spe__synth_data_source_default(record, &data_src); else arm_spe__synth_data_source_generic(record, &data_src); -- 2.34.1