From: Dapeng Mi <dapeng1.mi@linux.intel.com>
To: Sean Christopherson <seanjc@google.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Peter Zijlstra <peterz@infradead.org>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Kan Liang <kan.liang@linux.intel.com>,
Like Xu <likexu@tencent.com>, Mark Rutland <mark.rutland@arm.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Jiri Olsa <jolsa@kernel.org>, Namhyung Kim <namhyung@kernel.org>,
Ian Rogers <irogers@google.com>,
Adrian Hunter <adrian.hunter@intel.com>
Cc: kvm@vger.kernel.org, linux-perf-users@vger.kernel.org,
linux-kernel@vger.kernel.org,
Zhenyu Wang <zhenyuw@linux.intel.com>,
Zhang Xiong <xiong.y.zhang@intel.com>,
Lv Zhiyuan <zhiyuan.lv@intel.com>,
Yang Weijiang <weijiang.yang@intel.com>,
Dapeng Mi <dapeng1.mi@intel.com>,
Dapeng Mi <dapeng1.mi@linux.intel.com>
Subject: [PATCH RFC v3 06/13] perf/x86: Fix typos and inconsistent indents in perf_event header
Date: Tue, 22 Aug 2023 13:11:33 +0800 [thread overview]
Message-ID: <20230822051140.512879-7-dapeng1.mi@linux.intel.com> (raw)
In-Reply-To: <20230822051140.512879-1-dapeng1.mi@linux.intel.com>
There is one typo and some inconsistent indents in perf_event.h header
file. Fix them.
Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
---
arch/x86/include/asm/perf_event.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
index 85a9fd5a3ec3..63e1ce1f4b27 100644
--- a/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -386,15 +386,15 @@ static inline bool is_topdown_idx(int idx)
*
* With this fake counter assigned, the guest LBR event user (such as KVM),
* can program the LBR registers on its own, and we don't actually do anything
- * with then in the host context.
+ * with them in the host context.
*/
-#define INTEL_PMC_IDX_FIXED_VLBR (GLOBAL_STATUS_LBRS_FROZEN_BIT)
+#define INTEL_PMC_IDX_FIXED_VLBR (GLOBAL_STATUS_LBRS_FROZEN_BIT)
/*
* Pseudo-encoding the guest LBR event as event=0x00,umask=0x1b,
* since it would claim bit 58 which is effectively Fixed26.
*/
-#define INTEL_FIXED_VLBR_EVENT 0x1b00
+#define INTEL_FIXED_VLBR_EVENT 0x1b00
/*
* Adaptive PEBS v4
--
2.34.1
next prev parent reply other threads:[~2023-08-22 5:06 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-22 5:11 [PATCH RFC v3 00/13] Enable fixed counter 3 and topdown perf metrics for vPMU Dapeng Mi
2023-08-22 5:11 ` [PATCH RFC v3 01/13] KVM: x86/pmu: Add Intel CPUID-hinted TopDown slots event Dapeng Mi
2023-08-22 5:11 ` [PATCH RFC v3 02/13] KVM: x86/pmu: Support PMU fixed counter 3 Dapeng Mi
2023-08-22 5:11 ` [PATCH RFC v3 03/13] perf/core: Add function perf_event_group_leader_check() Dapeng Mi
2023-08-22 5:11 ` [PATCH RFC v3 04/13] perf/core: Add function perf_event_move_group() Dapeng Mi
2023-08-22 5:11 ` [PATCH RFC v3 05/13] perf/core: Add *group_leader for perf_event_create_group_kernel_counters() Dapeng Mi
2023-08-22 5:11 ` Dapeng Mi [this message]
2023-08-22 5:11 ` [PATCH RFC v3 07/13] perf/x86: Add constraint for guest perf metrics event Dapeng Mi
2023-08-22 5:11 ` [PATCH RFC v3 08/13] perf/core: Add new function perf_event_topdown_metrics() Dapeng Mi
2023-08-22 5:11 ` [PATCH RFC v3 09/13] perf/x86/intel: Handle KVM virtual metrics event in perf system Dapeng Mi
2023-08-22 5:11 ` [PATCH RFC v3 10/13] KVM: x86/pmu: Extend pmc_reprogram_counter() to create group events Dapeng Mi
2023-08-22 5:11 ` [PATCH RFC v3 11/13] KVM: x86/pmu: Support topdown perf metrics feature Dapeng Mi
2023-08-22 5:11 ` [PATCH RFC v3 12/13] KVM: x86/pmu: Handle PERF_METRICS overflow Dapeng Mi
2023-08-22 5:11 ` [PATCH RFC v3 13/13] KVM: x86/pmu: Expose Topdown in MSR_IA32_PERF_CAPABILITIES Dapeng Mi
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