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Fri, 15 Sep 2023 22:14:37 -0700 (PDT) Date: Fri, 15 Sep 2023 22:13:08 -0700 In-Reply-To: <20230916051310.1124098-1-irogers@google.com> Message-Id: <20230916051310.1124098-2-irogers@google.com> Mime-Version: 1.0 References: <20230916051310.1124098-1-irogers@google.com> X-Mailer: git-send-email 2.42.0.459.ge4e396fd5e-goog Subject: [PATCH v1 2/4] perf vendor events intel: Update alderlake events to v1.22 From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Ian Rogers , Adrian Hunter , Maxime Coquelin , Alexandre Torgue , Kan Liang , Zhengjun Xing , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Edward Baker Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-perf-users@vger.kernel.org v1.22 was released in: https://github.com/intel/perfmon/commit/846bd247c6e04acc572ca56c992e9e65852= bbe63 Update created using: https://github.com/intel/perfmon/blob/main/scripts/create_perf_json.py Signed-off-by: Ian Rogers --- .../arch/x86/alderlake/frontend.json | 42 ++++++++++-- .../pmu-events/arch/x86/alderlake/memory.json | 4 +- .../x86/alderlake/uncore-interconnect.json | 2 + .../arch/x86/alderlaken/memory.json | 4 +- .../x86/alderlaken/uncore-interconnect.json | 66 +++++++++++++++++++ tools/perf/pmu-events/arch/x86/mapfile.csv | 4 +- 6 files changed, 110 insertions(+), 12 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/alderlake/frontend.json b/tools= /perf/pmu-events/arch/x86/alderlake/frontend.json index 81349100fe32..542ba4a81996 100644 --- a/tools/perf/pmu-events/arch/x86/alderlake/frontend.json +++ b/tools/perf/pmu-events/arch/x86/alderlake/frontend.json @@ -394,31 +394,61 @@ "Unit": "cpu_core" }, { - "BriefDescription": "Uops not delivered by IDQ when backend of the= machine is not stalled", + "BriefDescription": "Uops not delivered by IDQ when backend of the= machine is not stalled [This event is alias to IDQ_UOPS_NOT_DELIVERED.CORE= ]", + "EventCode": "0x9c", + "EventName": "IDQ_BUBBLES.CORE", + "PublicDescription": "Counts the number of uops not delivered to b= y the Instruction Decode Queue (IDQ) to the back-end of the pipeline when t= here was no back-end stalls. This event counts for one SMT thread in a give= n cycle. [This event is alias to IDQ_UOPS_NOT_DELIVERED.CORE]", + "SampleAfterValue": "1000003", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Cycles when no uops are not delivered by the = IDQ when backend of the machine is not stalled [This event is alias to IDQ_= UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE]", + "CounterMask": "6", + "EventCode": "0x9c", + "EventName": "IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE", + "PublicDescription": "Counts the number of cycles when no uops wer= e delivered by the Instruction Decode Queue (IDQ) to the back-end of the pi= peline when there was no back-end stalls. This event counts for one SMT thr= ead in a given cycle. [This event is alias to IDQ_UOPS_NOT_DELIVERED.CYCLES= _0_UOPS_DELIV.CORE]", + "SampleAfterValue": "1000003", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Cycles when optimal number of uops was delive= red to the back-end when the back-end is not stalled [This event is alias t= o IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK]", + "CounterMask": "1", + "EventCode": "0x9c", + "EventName": "IDQ_BUBBLES.CYCLES_FE_WAS_OK", + "Invert": "1", + "PublicDescription": "Counts the number of cycles when the optimal= number of uops were delivered by the Instruction Decode Queue (IDQ) to the= back-end of the pipeline when there was no back-end stalls. This event cou= nts for one SMT thread in a given cycle. [This event is alias to IDQ_UOPS_N= OT_DELIVERED.CYCLES_FE_WAS_OK]", + "SampleAfterValue": "1000003", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Uops not delivered by IDQ when backend of the= machine is not stalled [This event is alias to IDQ_BUBBLES.CORE]", "EventCode": "0x9c", "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", - "PublicDescription": "Counts the number of uops not delivered to b= y the Instruction Decode Queue (IDQ) to the back-end of the pipeline when t= here was no back-end stalls. This event counts for one SMT thread in a give= n cycle.", + "PublicDescription": "Counts the number of uops not delivered to b= y the Instruction Decode Queue (IDQ) to the back-end of the pipeline when t= here was no back-end stalls. This event counts for one SMT thread in a give= n cycle. [This event is alias to IDQ_BUBBLES.CORE]", "SampleAfterValue": "1000003", "UMask": "0x1", "Unit": "cpu_core" }, { - "BriefDescription": "Cycles when no uops are not delivered by the = IDQ when backend of the machine is not stalled", + "BriefDescription": "Cycles when no uops are not delivered by the = IDQ when backend of the machine is not stalled [This event is alias to IDQ_= BUBBLES.CYCLES_0_UOPS_DELIV.CORE]", "CounterMask": "6", "EventCode": "0x9c", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", - "PublicDescription": "Counts the number of cycles when no uops wer= e delivered by the Instruction Decode Queue (IDQ) to the back-end of the pi= peline when there was no back-end stalls. This event counts for one SMT thr= ead in a given cycle.", + "PublicDescription": "Counts the number of cycles when no uops wer= e delivered by the Instruction Decode Queue (IDQ) to the back-end of the pi= peline when there was no back-end stalls. This event counts for one SMT thr= ead in a given cycle. [This event is alias to IDQ_BUBBLES.CYCLES_0_UOPS_DEL= IV.CORE]", "SampleAfterValue": "1000003", "UMask": "0x1", "Unit": "cpu_core" }, { - "BriefDescription": "Cycles when optimal number of uops was delive= red to the back-end when the back-end is not stalled", + "BriefDescription": "Cycles when optimal number of uops was delive= red to the back-end when the back-end is not stalled [This event is alias t= o IDQ_BUBBLES.CYCLES_FE_WAS_OK]", "CounterMask": "1", "EventCode": "0x9c", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", "Invert": "1", - "PublicDescription": "Counts the number of cycles when the optimal= number of uops were delivered by the Instruction Decode Queue (IDQ) to the= back-end of the pipeline when there was no back-end stalls. This event cou= nts for one SMT thread in a given cycle.", + "PublicDescription": "Counts the number of cycles when the optimal= number of uops were delivered by the Instruction Decode Queue (IDQ) to the= back-end of the pipeline when there was no back-end stalls. This event cou= nts for one SMT thread in a given cycle. [This event is alias to IDQ_BUBBLE= S.CYCLES_FE_WAS_OK]", "SampleAfterValue": "1000003", "UMask": "0x1", "Unit": "cpu_core" diff --git a/tools/perf/pmu-events/arch/x86/alderlake/memory.json b/tools/p= erf/pmu-events/arch/x86/alderlake/memory.json index 73d92d5c9f9d..23d36164433f 100644 --- a/tools/perf/pmu-events/arch/x86/alderlake/memory.json +++ b/tools/perf/pmu-events/arch/x86/alderlake/memory.json @@ -248,7 +248,7 @@ "Unit": "cpu_core" }, { - "BriefDescription": "Counts demand data reads that were not suppli= ed by the L3 cache.", + "BriefDescription": "Counts demand data reads that were not suppli= ed by the L3 cache. [L3_MISS_LOCAL is alias to L3_MISS]", "EventCode": "0xB7", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -278,7 +278,7 @@ "Unit": "cpu_core" }, { - "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were not suppli= ed by the L3 cache.", + "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were not suppli= ed by the L3 cache. [L3_MISS_LOCAL is alias to L3_MISS]", "EventCode": "0xB7", "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", diff --git a/tools/perf/pmu-events/arch/x86/alderlake/uncore-interconnect.j= son b/tools/perf/pmu-events/arch/x86/alderlake/uncore-interconnect.json index 34fc052d00e4..8bf020a9dfa8 100644 --- a/tools/perf/pmu-events/arch/x86/alderlake/uncore-interconnect.json +++ b/tools/perf/pmu-events/arch/x86/alderlake/uncore-interconnect.json @@ -25,6 +25,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_ARB_REQ_TRK_REQUEST.DRD", + "Deprecated": "1", "EventCode": "0x81", "EventName": "UNC_ARB_DAT_REQUESTS.RD", "PerPkg": "1", @@ -33,6 +34,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_ARB_DAT_OCCUPANCY.ALL", + "Deprecated": "1", "EventCode": "0x85", "EventName": "UNC_ARB_IFA_OCCUPANCY.ALL", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/alderlaken/memory.json b/tools/= perf/pmu-events/arch/x86/alderlaken/memory.json index 37259d38a222..863a3ba2b4b2 100644 --- a/tools/perf/pmu-events/arch/x86/alderlaken/memory.json +++ b/tools/perf/pmu-events/arch/x86/alderlaken/memory.json @@ -59,7 +59,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts demand data reads that were not suppli= ed by the L3 cache.", + "BriefDescription": "Counts demand data reads that were not suppli= ed by the L3 cache. [L3_MISS_LOCAL is alias to L3_MISS]", "EventCode": "0xB7", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -77,7 +77,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were not suppli= ed by the L3 cache.", + "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were not suppli= ed by the L3 cache. [L3_MISS_LOCAL is alias to L3_MISS]", "EventCode": "0xB7", "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", diff --git a/tools/perf/pmu-events/arch/x86/alderlaken/uncore-interconnect.= json b/tools/perf/pmu-events/arch/x86/alderlaken/uncore-interconnect.json index 4af695a5e755..8bf020a9dfa8 100644 --- a/tools/perf/pmu-events/arch/x86/alderlaken/uncore-interconnect.json +++ b/tools/perf/pmu-events/arch/x86/alderlaken/uncore-interconnect.json @@ -7,6 +7,56 @@ "UMask": "0x1", "Unit": "ARB" }, + { + "BriefDescription": "Each cycle counts number of any coherent requ= est at memory controller that were issued by any core.", + "EventCode": "0x85", + "EventName": "UNC_ARB_DAT_OCCUPANCY.ALL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "ARB" + }, + { + "BriefDescription": "Each cycle counts number of coherent reads pe= nding on data return from memory controller that were issued by any core.", + "EventCode": "0x85", + "EventName": "UNC_ARB_DAT_OCCUPANCY.RD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "ARB" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_ARB_REQ_TRK_REQUEST.DRD", + "Deprecated": "1", + "EventCode": "0x81", + "EventName": "UNC_ARB_DAT_REQUESTS.RD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "ARB" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = UNC_ARB_DAT_OCCUPANCY.ALL", + "Deprecated": "1", + "EventCode": "0x85", + "EventName": "UNC_ARB_IFA_OCCUPANCY.ALL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "ARB" + }, + { + "BriefDescription": "Each cycle count number of 'valid' coherent D= ata Read entries . Such entry is defined as valid when it is allocated till= deallocation. Doesn't include prefetches [This event is alias to UNC_ARB_T= RK_OCCUPANCY.RD]", + "EventCode": "0x80", + "EventName": "UNC_ARB_REQ_TRK_OCCUPANCY.DRD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "ARB" + }, + { + "BriefDescription": "Number of all coherent Data Read entries. Doe= sn't include prefetches [This event is alias to UNC_ARB_TRK_REQUESTS.RD]", + "EventCode": "0x81", + "EventName": "UNC_ARB_REQ_TRK_REQUEST.DRD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "ARB" + }, { "BriefDescription": "Each cycle counts number of all outgoing vali= d entries in ReqTrk. Such entry is defined as valid from its allocation in = ReqTrk till deallocation. Accounts for Coherent and non-coherent traffic.", "EventCode": "0x80", @@ -15,6 +65,14 @@ "UMask": "0x1", "Unit": "ARB" }, + { + "BriefDescription": "Each cycle count number of 'valid' coherent D= ata Read entries . Such entry is defined as valid when it is allocated till= deallocation. Doesn't include prefetches [This event is alias to UNC_ARB_R= EQ_TRK_OCCUPANCY.DRD]", + "EventCode": "0x80", + "EventName": "UNC_ARB_TRK_OCCUPANCY.RD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "ARB" + }, { "BriefDescription": "Counts the number of coherent and in-coherent= requests initiated by IA cores, processor graphic units, or LLC.", "EventCode": "0x81", @@ -22,5 +80,13 @@ "PerPkg": "1", "UMask": "0x1", "Unit": "ARB" + }, + { + "BriefDescription": "Number of all coherent Data Read entries. Doe= sn't include prefetches [This event is alias to UNC_ARB_REQ_TRK_REQUEST.DRD= ]", + "EventCode": "0x81", + "EventName": "UNC_ARB_TRK_REQUESTS.RD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "ARB" } ] diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index 51c64ac2b9f7..24f03cd804f6 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -1,6 +1,6 @@ Family-model,Version,Filename,EventType -GenuineIntel-6-(97|9A|B7|BA|BF),v1.21,alderlake,core -GenuineIntel-6-BE,v1.21,alderlaken,core +GenuineIntel-6-(97|9A|B7|BA|BF),v1.22,alderlake,core +GenuineIntel-6-BE,v1.22,alderlaken,core GenuineIntel-6-(1C|26|27|35|36),v5,bonnell,core GenuineIntel-6-(3D|47),v28,broadwell,core GenuineIntel-6-56,v11,broadwellde,core --=20 2.42.0.459.ge4e396fd5e-goog