From: Yu Chien Peter Lin <peterlin@andestech.com>
To: <acme@kernel.org>, <adrian.hunter@intel.com>,
<ajones@ventanamicro.com>, <alexander.shishkin@linux.intel.com>,
<andre.przywara@arm.com>, <anup@brainfault.org>,
<aou@eecs.berkeley.edu>, <atishp@atishpatra.org>,
<conor+dt@kernel.org>, <conor.dooley@microchip.com>,
<conor@kernel.org>, <devicetree@vger.kernel.org>,
<dminus@andestech.com>, <evan@rivosinc.com>,
<geert+renesas@glider.be>, <guoren@kernel.org>, <heiko@sntech.de>,
<irogers@google.com>, <jernej.skrabec@gmail.com>,
<jolsa@kernel.org>, <jszhang@kernel.org>,
<krzysztof.kozlowski+dt@linaro.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>,
<linux-perf-users@vger.kernel.org>,
<linux-renesas-soc@vger.kernel.org>,
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<locus84@andestech.com>, <magnus.damm@gmail.com>,
<mark.rutland@arm.com>, <mingo@redhat.com>, <n.shubin@yadro.com>,
<namhyung@kernel.org>, <palmer@dabbelt.com>,
<paul.walmsley@sifive.com>, <peterlin@andestech.com>,
<peterz@infradead.org>, <prabhakar.mahadev-lad.rj@bp.renesas.com>,
<rdunlap@infradead.org>, <robh+dt@kernel.org>,
<samuel@sholland.org>, <sunilvl@ventanamicro.com>,
<tglx@linutronix.de>, <tim609@andestech.com>, <uwu@icenowy.me>,
<wens@csie.org>, <will@kernel.org>, <ycliang@andestech.com>
Subject: [RFC PATCH v3 02/13] irqchip/riscv-intc: Allow large non-standard hwirq number
Date: Sun, 22 Oct 2023 23:18:47 +0800 [thread overview]
Message-ID: <20231022151858.2479969-3-peterlin@andestech.com> (raw)
In-Reply-To: <20231022151858.2479969-1-peterlin@andestech.com>
Currently, the implementation of the RISC-V INTC driver uses the
interrupt cause as hwirq and has a limitation of supporting a
maximum of 64 hwirqs. However, according to the privileged spec,
interrupt causes >= 16 are defined for platform use.
This limitation prevents us from fully utilizing the available
local interrupt sources. Additionally, the hwirqs used on RISC-V
are sparse, with only interrupt numbers 1, 5 and 9 (plus Sscofpmf
or T-Head's PMU irq) being currently used for supervisor mode.
The patch switches to using irq_domain_create_tree() which
creates the radix tree map, allowing us to handle a larger
number of hwirqs.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Charles Ci-Jyun Wu <dminus@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
---
Changes v1 -> v2:
- Fixed irq mapping failure checking (suggested by Clément and Anup)
Changes v2 -> v3:
- No change
---
drivers/irqchip/irq-riscv-intc.c | 12 ++++--------
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c
index e8d01b14ccdd..79d049105384 100644
--- a/drivers/irqchip/irq-riscv-intc.c
+++ b/drivers/irqchip/irq-riscv-intc.c
@@ -24,10 +24,8 @@ static asmlinkage void riscv_intc_irq(struct pt_regs *regs)
{
unsigned long cause = regs->cause & ~CAUSE_IRQ_FLAG;
- if (unlikely(cause >= BITS_PER_LONG))
- panic("unexpected interrupt cause");
-
- generic_handle_domain_irq(intc_domain, cause);
+ if (generic_handle_domain_irq(intc_domain, cause))
+ pr_warn("Failed to handle interrupt (cause: %ld)\n", cause);
}
/*
@@ -117,8 +115,8 @@ static int __init riscv_intc_init_common(struct fwnode_handle *fn)
{
int rc;
- intc_domain = irq_domain_create_linear(fn, BITS_PER_LONG,
- &riscv_intc_domain_ops, NULL);
+ intc_domain = irq_domain_create_tree(fn, &riscv_intc_domain_ops,
+ NULL);
if (!intc_domain) {
pr_err("unable to add IRQ domain\n");
return -ENXIO;
@@ -132,8 +130,6 @@ static int __init riscv_intc_init_common(struct fwnode_handle *fn)
riscv_set_intc_hwnode_fn(riscv_intc_hwnode);
- pr_info("%d local interrupts mapped\n", BITS_PER_LONG);
-
return 0;
}
--
2.34.1
next prev parent reply other threads:[~2023-10-22 15:24 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-22 15:18 [PATCH v3 00/13] Support Andes PMU extension Yu Chien Peter Lin
2023-10-22 15:18 ` [PATCH v3 01/13] riscv: errata: Rename defines for Andes Yu Chien Peter Lin
2023-10-22 15:18 ` Yu Chien Peter Lin [this message]
2023-10-22 15:18 ` [RFC PATCH v3 03/13] irqchip/riscv-intc: Introduce Andes IRQ chip Yu Chien Peter Lin
2023-10-22 15:18 ` [PATCH v3 04/13] dt-bindings: riscv: Add Andes interrupt controller compatible string Yu Chien Peter Lin
2023-10-22 15:18 ` [PATCH v3 05/13] riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes INTC Yu Chien Peter Lin
2023-10-22 18:00 ` [PATCH v3 00/13] Support Andes PMU extension Conor Dooley
2023-10-23 0:13 ` Yu-Chien Peter Lin
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