From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 28C80101E7; Sun, 22 Oct 2023 15:24:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=none Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3B7718E; Sun, 22 Oct 2023 08:24:22 -0700 (PDT) Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 39MFMTJX032707; Sun, 22 Oct 2023 23:22:29 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Sun, 22 Oct 2023 23:22:25 +0800 From: Yu Chien Peter Lin To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [RFC PATCH v3 03/13] irqchip/riscv-intc: Introduce Andes IRQ chip Date: Sun, 22 Oct 2023 23:18:48 +0800 Message-ID: <20231022151858.2479969-4-peterlin@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231022151858.2479969-1-peterlin@andestech.com> References: <20231022151858.2479969-1-peterlin@andestech.com> Precedence: bulk X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.0.15.183] X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL:Atcsqr.andestech.com 39MFMTJX032707 This commit adds support for the Andes IRQ chip, which provides IRQ mask/unmask functions to access the custom CSR (SLIE) where the non-standard S-mode local interrupt enable bits are located. The Andes INTC requires the "andestech,cpu-intc" compatible string to be present in interrupt-controller of cpu node. e.g., cpu0: cpu@0 { compatible = "andestech,ax45mp", "riscv"; ... cpu0-intc: interrupt-controller { #interrupt-cells = <0x01>; compatible = "andestech,cpu-intc", "riscv,cpu-intc"; interrupt-controller; }; }; Signed-off-by: Yu Chien Peter Lin Reviewed-by: Charles Ci-Jyun Wu Reviewed-by: Leo Yu-Chi Liang --- Changes v1 -> v2: - New patch Changes v2 -> v3: - Return -ENXIO if no valid compatible INTC found - Allow falling back to generic RISC-V INTC --- drivers/irqchip/irq-riscv-intc.c | 51 +++++++++++++++++++++++++- include/linux/irqchip/irq-riscv-intc.h | 12 ++++++ 2 files changed, 61 insertions(+), 2 deletions(-) create mode 100644 include/linux/irqchip/irq-riscv-intc.h diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c index 79d049105384..a0efd645a142 100644 --- a/drivers/irqchip/irq-riscv-intc.c +++ b/drivers/irqchip/irq-riscv-intc.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -45,6 +46,26 @@ static void riscv_intc_irq_unmask(struct irq_data *d) csr_set(CSR_IE, BIT(d->hwirq)); } +static void andes_intc_irq_mask(struct irq_data *d) +{ + unsigned int mask = BIT(d->hwirq % BITS_PER_LONG); + + if (d->hwirq < ANDES_SLI_CAUSE_BASE) + csr_clear(CSR_IE, mask); + else + csr_clear(ANDES_CSR_SLIE, mask); +} + +static void andes_intc_irq_unmask(struct irq_data *d) +{ + unsigned int mask = BIT(d->hwirq % BITS_PER_LONG); + + if (d->hwirq < ANDES_SLI_CAUSE_BASE) + csr_set(CSR_IE, mask); + else + csr_set(ANDES_CSR_SLIE, mask); +} + static void riscv_intc_irq_eoi(struct irq_data *d) { /* @@ -68,12 +89,37 @@ static struct irq_chip riscv_intc_chip = { .irq_eoi = riscv_intc_irq_eoi, }; +static struct irq_chip andes_intc_chip = { + .name = "RISC-V INTC", + .irq_mask = andes_intc_irq_mask, + .irq_unmask = andes_intc_irq_unmask, + .irq_eoi = riscv_intc_irq_eoi, +}; + static int riscv_intc_domain_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hwirq) { + struct fwnode_handle *fn = riscv_get_intc_hwnode(); + struct irq_chip *chip; + const char *cp; + int rc; + irq_set_percpu_devid(irq); - irq_domain_set_info(d, irq, hwirq, &riscv_intc_chip, d->host_data, - handle_percpu_devid_irq, NULL, NULL); + + rc = fwnode_property_read_string(fn, "compatible", &cp); + if (rc) + return rc; + + if (strcmp(cp, "riscv,cpu-intc") == 0) + chip = &riscv_intc_chip; + else if (strcmp(cp, "andestech,cpu-intc") == 0) + chip = &andes_intc_chip; + else + return -ENXIO; + + irq_domain_set_info(d, irq, hwirq, chip, + d->host_data, handle_percpu_devid_irq, NULL, + NULL); return 0; } @@ -166,6 +212,7 @@ static int __init riscv_intc_init(struct device_node *node, } IRQCHIP_DECLARE(riscv, "riscv,cpu-intc", riscv_intc_init); +IRQCHIP_DECLARE(andes, "andestech,cpu-intc", riscv_intc_init); #ifdef CONFIG_ACPI diff --git a/include/linux/irqchip/irq-riscv-intc.h b/include/linux/irqchip/irq-riscv-intc.h new file mode 100644 index 000000000000..87c105b5b545 --- /dev/null +++ b/include/linux/irqchip/irq-riscv-intc.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2023 Andes Technology Corporation + */ +#ifndef __INCLUDE_LINUX_IRQCHIP_IRQ_RISCV_INTC_H +#define __INCLUDE_LINUX_IRQCHIP_IRQ_RISCV_INTC_H + +#define ANDES_SLI_CAUSE_BASE 256 +#define ANDES_CSR_SLIE 0x9c4 +#define ANDES_CSR_SLIP 0x9c5 + +#endif /* __INCLUDE_LINUX_IRQCHIP_IRQ_RISCV_INTC_H */ -- 2.34.1