From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8B9C018629; Mon, 23 Oct 2023 12:04:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="MY2dbfAS" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 42501C433C8; Mon, 23 Oct 2023 12:03:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1698062644; bh=n/SYhgOy7PYoOMa/qRT/xqvF+V6QNHFqWYg+hu0aDj4=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=MY2dbfASZER6tuIdGGsFhjcDL09IA9tXH1K2hRODqDJmoBwN1y9Pn+s7KPAjTz4yb 9JPo8v456haLAbc55KVPK4k05l3EDrlzlGgCg7itvHppqavF+wM3J5IreBTFzbhIfB kLQ24DWYhW6tANl7QVCqPNxPNSeWuykvVc7skyKlqMhb6XeBov4DJsAUrTf0Zkyszr MzoffD2wL1QGU5T/xqwnIIQzr0YFM0MC/Nh0v2A2Bu5EYeYXfKE6DHwygsEIlmRIyw AequAVKeZ4TbiC3hjQRz+JPCvpgJpmIy7hm8buNLxBNK59ViC3AYScv2oHmO7kX0eE YXqYt+lr/L2RQ== Date: Mon, 23 Oct 2023 13:03:53 +0100 From: Conor Dooley To: Yu Chien Peter Lin Cc: acme@kernel.org, adrian.hunter@intel.com, ajones@ventanamicro.com, alexander.shishkin@linux.intel.com, andre.przywara@arm.com, anup@brainfault.org, aou@eecs.berkeley.edu, atishp@atishpatra.org, conor+dt@kernel.org, conor.dooley@microchip.com, devicetree@vger.kernel.org, dminus@andestech.com, evan@rivosinc.com, geert+renesas@glider.be, guoren@kernel.org, heiko@sntech.de, irogers@google.com, jernej.skrabec@gmail.com, jolsa@kernel.org, jszhang@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-sunxi@lists.linux.dev, locus84@andestech.com, magnus.damm@gmail.com, mark.rutland@arm.com, mingo@redhat.com, n.shubin@yadro.com, namhyung@kernel.org, palmer@dabbelt.com, paul.walmsley@sifive.com, peterz@infradead.org, prabhakar.mahadev-lad.rj@bp.renesas.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, sunilvl@ventanamicro.com, tglx@linutronix.de, tim609@andestech.com, uwu@icenowy.me, wens@csie.org, will@kernel.org, ycliang@andestech.com Subject: Re: [PATCH v3 RESEND 10/13] dt-bindings: riscv: Add Andes PMU extension description Message-ID: <20231023-spectacle-module-0516fb35995a@spud> References: <20231023004100.2663486-1-peterlin@andestech.com> <20231023004100.2663486-11-peterlin@andestech.com> Precedence: bulk X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="P1S9GHX9rhzdHs0r" Content-Disposition: inline In-Reply-To: <20231023004100.2663486-11-peterlin@andestech.com> --P1S9GHX9rhzdHs0r Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Mon, Oct 23, 2023 at 08:40:57AM +0800, Yu Chien Peter Lin wrote: > Document the ISA string for Andes Technology performance monitor > extension which provides counter overflow interrupt and mode > filtering mechanisms. >=20 > Signed-off-by: Yu Chien Peter Lin > --- > Changes v2 -> v3: > - New patch > --- > Documentation/devicetree/bindings/riscv/extensions.yaml | 7 +++++++ > 1 file changed, 7 insertions(+) >=20 > diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Do= cumentation/devicetree/bindings/riscv/extensions.yaml > index 5e9291d258d5..e0694e2adbc2 100644 > --- a/Documentation/devicetree/bindings/riscv/extensions.yaml > +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml > @@ -246,6 +246,13 @@ properties: > in commit 2e5236 ("Ztso is now ratified.") of the > riscv-isa-manual. > =20 > + - const: xandespmu > + description: > + The Andes Technology performance monitor extension for count= er overflow > + and privilege mode filtering. For more details, see Counter = Related > + Registers in the AX45MP datasheet. > + https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-= 5.0.0-Datasheet.pdf Does/will this PMU function identically on the other CPUs that support it? I assume the answer is yes. Cheers, Conor. > + > - const: xtheadpmu > description: > The T-Head performance monitor extension for counter overflo= w. For more > --=20 > 2.34.1 >=20 --P1S9GHX9rhzdHs0r Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCZTZhKQAKCRB4tDGHoIJi 0q2MAP0VirheuKpWgXrPAEWaqZ66m6sp12MVuSOdCvU0US0f/AEA2BobNxX5Jk4Y UqRJn9N7kWZtJAvcqBjJPvvs15wdpgc= =/DQg -----END PGP SIGNATURE----- --P1S9GHX9rhzdHs0r--