From: Conor Dooley <conor@kernel.org>
To: Yu-Chien Peter Lin <peterlin@andestech.com>
Cc: Conor Dooley <conor.dooley@microchip.com>,
acme@kernel.org, adrian.hunter@intel.com,
ajones@ventanamicro.com, alexander.shishkin@linux.intel.com,
andre.przywara@arm.com, anup@brainfault.org,
aou@eecs.berkeley.edu, atishp@atishpatra.org,
conor+dt@kernel.org, devicetree@vger.kernel.org,
dminus@andestech.com, evan@rivosinc.com, geert+renesas@glider.be,
guoren@kernel.org, heiko@sntech.de, irogers@google.com,
jernej.skrabec@gmail.com, jolsa@kernel.org, jszhang@kernel.org,
krzysztof.kozlowski+dt@linaro.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
linux-renesas-soc@vger.kernel.org,
linux-riscv@lists.infradead.org, linux-sunxi@lists.linux.dev,
locus84@andestech.com, magnus.damm@gmail.com,
mark.rutland@arm.com, mingo@redhat.com, n.shubin@yadro.com,
namhyung@kernel.org, palmer@dabbelt.com,
paul.walmsley@sifive.com, peterz@infradead.org,
prabhakar.mahadev-lad.rj@bp.renesas.com, rdunlap@infradead.org,
robh+dt@kernel.org, samuel@sholland.org,
sunilvl@ventanamicro.com, tglx@linutronix.de,
tim609@andestech.com, uwu@icenowy.me, wens@csie.org,
will@kernel.org, ycliang@andestech.com, inochiama@outlook.com
Subject: Re: [PATCH v4 09/13] dt-bindings: riscv: Add T-Head PMU extension description
Date: Wed, 29 Nov 2023 12:33:46 +0000 [thread overview]
Message-ID: <20231129-curvature-stainable-bf77c735438f@spud> (raw)
In-Reply-To: <ZWb6qqaNzzNUJ7aX@APC323>
[-- Attachment #1: Type: text/plain, Size: 1787 bytes --]
On Wed, Nov 29, 2023 at 04:47:38PM +0800, Yu-Chien Peter Lin wrote:
> Hi Conor,
>
> On Thu, Nov 23, 2023 at 02:48:20PM +0000, Conor Dooley wrote:
> > On Wed, Nov 22, 2023 at 08:12:31PM +0800, Yu Chien Peter Lin wrote:
> > > Document the ISA string for T-Head performance monitor extension
> > > which provides counter overflow interrupt mechanism.
> > >
> > > Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> > > ---
> > > Changes v2 -> v3:
> > > - New patch
> > > Changes v3 -> v4:
> > > - No change
> > > ---
> > > Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++
> > > 1 file changed, 6 insertions(+)
> > >
> > > diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> > > index c91ab0e46648..694efaea8fce 100644
> > > --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> > > +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> > > @@ -258,5 +258,11 @@ properties:
> > > in commit 2e5236 ("Ztso is now ratified.") of the
> > > riscv-isa-manual.
> > >
> > > + - const: xtheadpmu
> > > + description:
> > > + The T-Head performance monitor extension for counter overflow. For more
> > > + details, see the chapter 12 in the Xuantie C906 user manual.
> > > + https://github.com/T-head-Semi/openc906/tree/main/doc
> >
> > I'm pretty sure that I asked on the previous revision for you to
> > identify a specific revision of this document.
>
> Sorry, I'm still searching for it.
Identifying a specific commit from that repo as the revision would be
okay. Follow the format used elsewhere for the standard extensions.
Cheers,
Conor.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
next prev parent reply other threads:[~2023-11-29 12:33 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-22 12:12 [PATCH v4 00/13] Support Andes PMU extension Yu Chien Peter Lin
2023-11-22 12:12 ` [PATCH v4 01/13] riscv: errata: Rename defines for Andes Yu Chien Peter Lin
2023-11-24 14:57 ` Lad, Prabhakar
2023-11-22 12:12 ` [PATCH v4 02/13] irqchip/riscv-intc: Allow large non-standard interrupt number Yu Chien Peter Lin
2023-12-08 15:54 ` Thomas Gleixner
2023-12-12 10:17 ` Yu-Chien Peter Lin
2023-11-22 12:12 ` [PATCH v4 03/13] irqchip/riscv-intc: Introduce Andes hart-level interrupt controller Yu Chien Peter Lin
2023-12-08 16:01 ` Thomas Gleixner
2023-12-12 10:28 ` Yu-Chien Peter Lin
2023-11-22 12:12 ` [PATCH v4 04/13] dt-bindings: riscv: Add Andes interrupt controller compatible string Yu Chien Peter Lin
2023-11-23 14:38 ` Conor Dooley
2023-11-24 15:03 ` Lad, Prabhakar
2023-11-24 15:05 ` Conor Dooley
2023-11-29 6:43 ` Yu-Chien Peter Lin
2023-11-22 12:12 ` [PATCH v4 05/13] riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes INTC Yu Chien Peter Lin
2023-11-22 16:36 ` Geert Uytterhoeven
2023-11-24 15:04 ` Lad, Prabhakar
2023-11-22 12:12 ` [PATCH v4 06/13] perf: RISC-V: Eliminate redundant interrupt enable/disable operations Yu Chien Peter Lin
2023-11-22 12:12 ` [PATCH v4 07/13] RISC-V: Move T-Head PMU to CPU feature alternative framework Yu Chien Peter Lin
2023-11-22 21:16 ` Guo Ren
2023-11-23 14:45 ` Conor Dooley
2023-11-22 12:12 ` [PATCH v4 08/13] perf: RISC-V: Introduce Andes PMU for perf event sampling Yu Chien Peter Lin
2023-11-24 15:06 ` Lad, Prabhakar
2023-11-22 12:12 ` [PATCH v4 09/13] dt-bindings: riscv: Add T-Head PMU extension description Yu Chien Peter Lin
2023-11-22 21:14 ` Guo Ren
2023-11-29 8:48 ` Yu-Chien Peter Lin
2023-11-30 8:29 ` Inochi Amaoto
2023-11-30 9:21 ` Yu-Chien Peter Lin
2023-11-30 12:16 ` Inochi Amaoto
2023-11-30 12:58 ` Conor Dooley
2023-11-30 23:11 ` Inochi Amaoto
2023-12-01 0:40 ` Conor Dooley
2023-12-01 0:57 ` Inochi Amaoto
2023-12-01 1:14 ` Inochi Amaoto
2023-12-06 3:14 ` Yu-Chien Peter Lin
2023-11-23 14:48 ` Conor Dooley
2023-11-29 8:47 ` Yu-Chien Peter Lin
2023-11-29 12:33 ` Conor Dooley [this message]
2023-11-22 12:12 ` [PATCH v4 10/13] dt-bindings: riscv: Add Andes " Yu Chien Peter Lin
2023-11-24 15:07 ` Lad, Prabhakar
2023-11-22 12:12 ` [PATCH v4 11/13] riscv: dts: allwinner: Add T-Head PMU extension Yu Chien Peter Lin
2023-11-22 21:12 ` Guo Ren
2023-11-23 14:58 ` Conor Dooley
2023-11-29 9:34 ` Yu-Chien Peter Lin
2023-11-22 12:12 ` [PATCH v4 12/13] riscv: dts: renesas: Add Andes " Yu Chien Peter Lin
2023-11-22 16:34 ` Geert Uytterhoeven
2023-11-24 15:07 ` Lad, Prabhakar
2023-11-22 12:12 ` [PATCH v4 13/13] riscv: andes: Support symbolic FW and HW raw events Yu Chien Peter Lin
2023-11-24 15:08 ` Lad, Prabhakar
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20231129-curvature-stainable-bf77c735438f@spud \
--to=conor@kernel.org \
--cc=acme@kernel.org \
--cc=adrian.hunter@intel.com \
--cc=ajones@ventanamicro.com \
--cc=alexander.shishkin@linux.intel.com \
--cc=andre.przywara@arm.com \
--cc=anup@brainfault.org \
--cc=aou@eecs.berkeley.edu \
--cc=atishp@atishpatra.org \
--cc=conor+dt@kernel.org \
--cc=conor.dooley@microchip.com \
--cc=devicetree@vger.kernel.org \
--cc=dminus@andestech.com \
--cc=evan@rivosinc.com \
--cc=geert+renesas@glider.be \
--cc=guoren@kernel.org \
--cc=heiko@sntech.de \
--cc=inochiama@outlook.com \
--cc=irogers@google.com \
--cc=jernej.skrabec@gmail.com \
--cc=jolsa@kernel.org \
--cc=jszhang@kernel.org \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-perf-users@vger.kernel.org \
--cc=linux-renesas-soc@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=linux-sunxi@lists.linux.dev \
--cc=locus84@andestech.com \
--cc=magnus.damm@gmail.com \
--cc=mark.rutland@arm.com \
--cc=mingo@redhat.com \
--cc=n.shubin@yadro.com \
--cc=namhyung@kernel.org \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
--cc=peterlin@andestech.com \
--cc=peterz@infradead.org \
--cc=prabhakar.mahadev-lad.rj@bp.renesas.com \
--cc=rdunlap@infradead.org \
--cc=robh+dt@kernel.org \
--cc=samuel@sholland.org \
--cc=sunilvl@ventanamicro.com \
--cc=tglx@linutronix.de \
--cc=tim609@andestech.com \
--cc=uwu@icenowy.me \
--cc=wens@csie.org \
--cc=will@kernel.org \
--cc=ycliang@andestech.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).