From: Conor Dooley <conor@kernel.org>
To: Yu Chien Peter Lin <peterlin@andestech.com>
Cc: acme@kernel.org, adrian.hunter@intel.com,
ajones@ventanamicro.com, alexander.shishkin@linux.intel.com,
andre.przywara@arm.com, anup@brainfault.org,
aou@eecs.berkeley.edu, atishp@atishpatra.org,
conor+dt@kernel.org, conor.dooley@microchip.com,
devicetree@vger.kernel.org, dminus@andestech.com,
evan@rivosinc.com, geert+renesas@glider.be, guoren@kernel.org,
heiko@sntech.de, irogers@google.com, jernej.skrabec@gmail.com,
jolsa@kernel.org, jszhang@kernel.org,
krzysztof.kozlowski+dt@linaro.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
linux-renesas-soc@vger.kernel.org,
linux-riscv@lists.infradead.org, linux-sunxi@lists.linux.dev,
locus84@andestech.com, magnus.damm@gmail.com,
mark.rutland@arm.com, mingo@redhat.com, n.shubin@yadro.com,
namhyung@kernel.org, palmer@dabbelt.com,
paul.walmsley@sifive.com, peterz@infradead.org,
prabhakar.mahadev-lad.rj@bp.renesas.com, rdunlap@infradead.org,
robh+dt@kernel.org, samuel@sholland.org,
sunilvl@ventanamicro.com, tglx@linutronix.de,
tim609@andestech.com, uwu@icenowy.me, wens@csie.org,
will@kernel.org, ycliang@andestech.com, inochiama@outlook.com
Subject: Re: [PATCH v5 09/16] dt-bindings: riscv: Add T-Head PMU extension description
Date: Wed, 13 Dec 2023 15:26:28 +0000 [thread overview]
Message-ID: <20231213-romp-squeegee-0cdb44aff415@spud> (raw)
In-Reply-To: <20231213070301.1684751-10-peterlin@andestech.com>
[-- Attachment #1: Type: text/plain, Size: 1722 bytes --]
On Wed, Dec 13, 2023 at 03:02:54PM +0800, Yu Chien Peter Lin wrote:
> Document the ISA string for T-Head performance monitor extension
> which provides counter overflow interrupt mechanism.
>
> Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> Reviewed-by: Guo Ren <guoren@kernel.org>
> Reviewed-by: Inochi Amaoto <inochiama@outlook.com>
> ---
> Changes v2 -> v3:
> - New patch
> Changes v3 -> v4:
> - No change
> Changes v4 -> v5:
> - Include Guo's Reviewed-by
> - Include Inochi's Reviewed-by
> - Update to C910 documentation with its commit hash
> ---
> Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> index c91ab0e46648..b5cb8ac7ac80 100644
> --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> @@ -258,5 +258,11 @@ properties:
> in commit 2e5236 ("Ztso is now ratified.") of the
> riscv-isa-manual.
>
> + - const: xtheadpmu
> + description:
> + The T-Head performance monitor extension for counter overflow, as ratified
I'm not sure that "ratified" here is the right word, probably
"documented" is better, but I don't think that is worth a resend.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Cheers,
Conor.
> + in commit 4c4981 ("Initial commit") of Xuantie C910 user manual.
> + https://github.com/T-head-Semi/openc910/tree/main/doc
> +
> additionalProperties: true
> ...
> --
> 2.34.1
>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
next prev parent reply other threads:[~2023-12-13 15:26 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-13 7:02 [PATCH v5 00/16] Support Andes PMU extension Yu Chien Peter Lin
2023-12-13 7:02 ` [PATCH v5 01/16] riscv: errata: Rename defines for Andes Yu Chien Peter Lin
2023-12-13 7:02 ` [PATCH v5 02/16] irqchip/riscv-intc: Allow large non-standard interrupt number Yu Chien Peter Lin
2023-12-13 14:28 ` Anup Patel
2023-12-13 15:19 ` Anup Patel
2023-12-19 7:43 ` Yu-Chien Peter Lin
2023-12-13 7:02 ` [PATCH v5 03/16] irqchip/riscv-intc: Introduce Andes hart-level interrupt controller Yu Chien Peter Lin
2023-12-13 14:45 ` Anup Patel
2023-12-13 15:44 ` Yu-Chien Peter Lin
2023-12-13 15:48 ` Anup Patel
2023-12-13 7:02 ` [PATCH v5 04/16] dt-bindings: riscv: Add Andes interrupt controller compatible string Yu Chien Peter Lin
2023-12-13 7:02 ` [PATCH v5 05/16] riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes INTC Yu Chien Peter Lin
2023-12-13 7:02 ` [PATCH v5 06/16] perf: RISC-V: Eliminate redundant interrupt enable/disable operations Yu Chien Peter Lin
2023-12-13 7:02 ` [PATCH v5 07/16] RISC-V: Move T-Head PMU to CPU feature alternative framework Yu Chien Peter Lin
2023-12-13 15:27 ` Conor Dooley
2023-12-13 15:32 ` Conor Dooley
2023-12-13 7:02 ` [PATCH v5 08/16] perf: RISC-V: Introduce Andes PMU for perf event sampling Yu Chien Peter Lin
2023-12-13 7:02 ` [PATCH v5 09/16] dt-bindings: riscv: Add T-Head PMU extension description Yu Chien Peter Lin
2023-12-13 15:26 ` Conor Dooley [this message]
2023-12-13 7:02 ` [PATCH v5 10/16] dt-bindings: riscv: Add Andes " Yu Chien Peter Lin
2023-12-13 7:02 ` [PATCH v5 11/16] riscv: dts: allwinner: Add T-Head PMU extension for sun20i-d1s Yu Chien Peter Lin
2023-12-13 7:02 ` [PATCH v5 12/16] riscv: dts: sophgo: Add T-Head PMU extension for cv1800b Yu Chien Peter Lin
2023-12-13 15:23 ` Conor Dooley
2023-12-13 7:02 ` [PATCH v5 13/16] riscv: dts: sophgo: Add T-Head PMU extension for sg2042 Yu Chien Peter Lin
2023-12-13 15:24 ` Conor Dooley
2023-12-13 7:02 ` [PATCH v5 14/16] riscv: dts: thead: Add T-Head PMU extension for th1520 Yu Chien Peter Lin
2023-12-13 15:23 ` Conor Dooley
2023-12-13 7:03 ` [PATCH v5 15/16] riscv: dts: renesas: Add Andes PMU extension for r9a07g043f Yu Chien Peter Lin
2023-12-13 15:24 ` Conor Dooley
2023-12-13 7:03 ` [PATCH v5 16/16] riscv: andes: Support specifying symbolic firmware and hardware raw events Yu Chien Peter Lin
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20231213-romp-squeegee-0cdb44aff415@spud \
--to=conor@kernel.org \
--cc=acme@kernel.org \
--cc=adrian.hunter@intel.com \
--cc=ajones@ventanamicro.com \
--cc=alexander.shishkin@linux.intel.com \
--cc=andre.przywara@arm.com \
--cc=anup@brainfault.org \
--cc=aou@eecs.berkeley.edu \
--cc=atishp@atishpatra.org \
--cc=conor+dt@kernel.org \
--cc=conor.dooley@microchip.com \
--cc=devicetree@vger.kernel.org \
--cc=dminus@andestech.com \
--cc=evan@rivosinc.com \
--cc=geert+renesas@glider.be \
--cc=guoren@kernel.org \
--cc=heiko@sntech.de \
--cc=inochiama@outlook.com \
--cc=irogers@google.com \
--cc=jernej.skrabec@gmail.com \
--cc=jolsa@kernel.org \
--cc=jszhang@kernel.org \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-perf-users@vger.kernel.org \
--cc=linux-renesas-soc@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=linux-sunxi@lists.linux.dev \
--cc=locus84@andestech.com \
--cc=magnus.damm@gmail.com \
--cc=mark.rutland@arm.com \
--cc=mingo@redhat.com \
--cc=n.shubin@yadro.com \
--cc=namhyung@kernel.org \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
--cc=peterlin@andestech.com \
--cc=peterz@infradead.org \
--cc=prabhakar.mahadev-lad.rj@bp.renesas.com \
--cc=rdunlap@infradead.org \
--cc=robh+dt@kernel.org \
--cc=samuel@sholland.org \
--cc=sunilvl@ventanamicro.com \
--cc=tglx@linutronix.de \
--cc=tim609@andestech.com \
--cc=uwu@icenowy.me \
--cc=wens@csie.org \
--cc=will@kernel.org \
--cc=ycliang@andestech.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).