From: Yu Chien Peter Lin <peterlin@andestech.com>
To: <acme@kernel.org>, <adrian.hunter@intel.com>,
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Subject: [PATCH v6 10/16] dt-bindings: riscv: Add Andes PMU extension description
Date: Mon, 25 Dec 2023 18:33:02 +0800 [thread overview]
Message-ID: <20231225103308.1557548-11-peterlin@andestech.com> (raw)
In-Reply-To: <20231225103308.1557548-1-peterlin@andestech.com>
Document the ISA string for Andes Technology performance monitor
extension which provides counter overflow interrupt and mode
filtering mechanisms.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
Changes v2 -> v3:
- New patch
Changes v3 -> v4:
- Include Conor's Acked-by
Changes v4 -> v5:
- Include Prabhakar's Reviewed-by
Changes v5 -> v6:
- No change
---
Documentation/devicetree/bindings/riscv/extensions.yaml | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index b5cb8ac7ac80..daef6c3b1580 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -258,6 +258,13 @@ properties:
in commit 2e5236 ("Ztso is now ratified.") of the
riscv-isa-manual.
+ - const: xandespmu
+ description:
+ The Andes Technology performance monitor extension for counter overflow
+ and privilege mode filtering. For more details, see Counter Related
+ Registers in the AX45MP datasheet.
+ https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf
+
- const: xtheadpmu
description:
The T-Head performance monitor extension for counter overflow, as ratified
--
2.34.1
next prev parent reply other threads:[~2023-12-25 10:48 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-25 10:32 [PATCH v6 00/16] Support Andes PMU extension Yu Chien Peter Lin
2023-12-25 10:32 ` [PATCH v6 01/16] riscv: errata: Rename defines for Andes Yu Chien Peter Lin
2023-12-25 10:32 ` [PATCH v6 02/16] irqchip/riscv-intc: Allow large non-standard interrupt number Yu Chien Peter Lin
2023-12-25 10:32 ` [PATCH v6 03/16] irqchip/riscv-intc: Introduce Andes hart-level interrupt controller Yu Chien Peter Lin
2023-12-25 10:32 ` [PATCH v6 04/16] dt-bindings: riscv: Add Andes interrupt controller compatible string Yu Chien Peter Lin
2023-12-25 10:32 ` [PATCH v6 05/16] riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes INTC Yu Chien Peter Lin
2023-12-25 10:32 ` [PATCH v6 06/16] perf: RISC-V: Eliminate redundant interrupt enable/disable operations Yu Chien Peter Lin
2023-12-25 10:32 ` [PATCH v6 07/16] RISC-V: Move T-Head PMU to CPU feature alternative framework Yu Chien Peter Lin
2023-12-25 10:33 ` [PATCH v6 08/16] perf: RISC-V: Introduce Andes PMU for perf event sampling Yu Chien Peter Lin
2023-12-25 10:33 ` [PATCH v6 09/16] dt-bindings: riscv: Add T-Head PMU extension description Yu Chien Peter Lin
2023-12-25 10:33 ` Yu Chien Peter Lin [this message]
2023-12-25 10:33 ` [PATCH v6 11/16] riscv: dts: allwinner: Add T-Head PMU extension for sun20i-d1s Yu Chien Peter Lin
2023-12-25 10:33 ` [PATCH v6 12/16] riscv: dts: sophgo: Add T-Head PMU extension for cv1800b Yu Chien Peter Lin
2023-12-25 10:33 ` [PATCH v6 13/16] riscv: dts: sophgo: Add T-Head PMU extension for sg2042 Yu Chien Peter Lin
2023-12-25 10:33 ` [PATCH v6 14/16] riscv: dts: thead: Add T-Head PMU extension for th1520 Yu Chien Peter Lin
2023-12-25 10:33 ` [PATCH v6 15/16] riscv: dts: renesas: Add Andes PMU extension for r9a07g043f Yu Chien Peter Lin
2023-12-25 10:33 ` [PATCH v6 16/16] riscv: andes: Support specifying symbolic firmware and hardware raw events Yu Chien Peter Lin
2023-12-25 21:06 ` [PATCH v6 00/16] Support Andes PMU extension Lad, Prabhakar
2023-12-26 2:59 ` Yu-Chien Peter Lin
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