From: Atish Patra <atishp@rivosinc.com>
To: linux-kernel@vger.kernel.org
Cc: "Atish Patra" <atishp@rivosinc.com>,
"Adrian Hunter" <adrian.hunter@intel.com>,
"Alexander Shishkin" <alexander.shishkin@linux.intel.com>,
"Alexandre Ghiti" <alexghiti@rivosinc.com>,
"Andrew Jones" <ajones@ventanamicro.com>,
"Anup Patel" <anup@brainfault.org>,
"Arnaldo Carvalho de Melo" <acme@kernel.org>,
"Atish Patra" <atishp@atishpatra.org>,
"Christian Brauner" <brauner@kernel.org>,
"Clément Léger" <cleger@rivosinc.com>,
"Conor Dooley" <conor@kernel.org>,
devicetree@vger.kernel.org, "Evan Green" <evan@rivosinc.com>,
"Guo Ren" <guoren@kernel.org>, "Heiko Stuebner" <heiko@sntech.de>,
"Ian Rogers" <irogers@google.com>,
"Ingo Molnar" <mingo@redhat.com>,
"James Clark" <james.clark@arm.com>,
"Jing Zhang" <renyu.zj@linux.alibaba.com>,
"Jiri Olsa" <jolsa@kernel.org>,
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"John Garry" <john.g.garry@oracle.com>,
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"Mark Rutland" <mark.rutland@arm.com>,
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Subject: [PATCH RFC 10/20] dt-bindings: riscv: add Smcntrpmf ISA extension description
Date: Fri, 16 Feb 2024 16:57:28 -0800 [thread overview]
Message-ID: <20240217005738.3744121-11-atishp@rivosinc.com> (raw)
In-Reply-To: <20240217005738.3744121-1-atishp@rivosinc.com>
Add the description for Smcntrpmf ISA extension
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
Documentation/devicetree/bindings/riscv/extensions.yaml | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index 15adeb60441b..149ecf2a8af3 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -135,6 +135,13 @@ properties:
directlyi accessible in the supervisor mode. This extension depend
on Sscsrind, Zihpm, Zicntr extensions.
+ - const: smcntrpmf
+ description: |
+ The standard Smcntrpmf supervisor-level extension for the machine mode
+ to enable privilege mode filtering for cycle and instret counters.
+ The Ssccfg extension depends on this as *cfg CSRs are available only
+ if smcntrpmf is present.
+
- const: smstateen
description: |
The standard Smstateen extension for controlling access to CSRs
--
2.34.1
next prev parent reply other threads:[~2024-02-17 0:58 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-17 0:57 [PATCH RFC 00/20] Add Counter delegation ISA extension support Atish Patra
2024-02-17 0:57 ` [PATCH RFC 01/20] perf pmu-events: Add functions in jevent.py to parse counter and event info for hardware aware grouping Atish Patra
2024-02-17 0:57 ` [PATCH RFC 02/20] RISC-V: Add Sxcsrind ISA extension CSR definitions Atish Patra
2024-02-17 0:57 ` [PATCH RFC 03/20] RISC-V: Add Sxcsrind ISA extension definition and parsing Atish Patra
2024-02-17 0:57 ` [PATCH RFC 04/20] dt-bindings: riscv: add Sxcsrind ISA extension description Atish Patra
2024-02-18 12:47 ` Conor Dooley
2024-02-17 0:57 ` [PATCH RFC 05/20] RISC-V: Define indirect CSR access helpers Atish Patra
2024-02-17 0:57 ` [PATCH RFC 06/20] RISC-V: Add Sscfg extension CSR definition Atish Patra
2024-02-17 0:57 ` [PATCH RFC 07/20] RISC-V: Add Ssccfg ISA extension definition and parsing Atish Patra
2024-02-17 0:57 ` [PATCH RFC 08/20] dt-bindings: riscv: add Ssccfg ISA extension description Atish Patra
2024-02-17 2:33 ` Rob Herring
2024-02-17 0:57 ` [PATCH RFC 09/20] RISC-V: Add Smcntrpmf extension parsing Atish Patra
2024-02-18 12:50 ` Conor Dooley
2024-02-17 0:57 ` Atish Patra [this message]
2024-02-17 2:33 ` [PATCH RFC 10/20] dt-bindings: riscv: add Smcntrpmf ISA extension description Rob Herring
2024-02-17 0:57 ` [PATCH RFC 11/20] RISC-V: perf: Restructure the SBI PMU code Atish Patra
2024-02-17 0:57 ` [PATCH RFC 12/20] RISC-V: perf: Modify the counter discovery mechanism Atish Patra
2024-02-17 0:57 ` [PATCH RFC 13/20] RISC-V: perf: Implement supervisor counter delegation support Atish Patra
2024-02-17 0:57 ` [PATCH RFC 14/20] RISC-V: perf: Use config2 for event to counter mapping Atish Patra
2024-02-17 0:57 ` [PATCH RFC 15/20] tools/perf: Add arch hooks to override perf standard events Atish Patra
2024-02-17 0:57 ` [PATCH RFC 16/20] tools/perf: Pass the Counter constraint values in the pmu events Atish Patra
2024-02-17 0:57 ` [PATCH RFC 17/20] perf: Add json file for virt machine supported events Atish Patra
2024-02-17 0:57 ` [PATCH RFC 18/20] tools arch uapi: Sync the uinstd.h header file for RISC-V Atish Patra
2024-02-17 0:57 ` [PATCH RFC 19/20] RISC-V: Add hwprobe support for Counter delegation extensions Atish Patra
2024-02-17 0:57 ` [PATCH RFC 20/20] tools/perf: Detect if platform supports counter delegation Atish Patra
2024-02-17 20:28 ` [PATCH RFC 00/20] Add Counter delegation ISA extension support Ian Rogers
2024-02-29 1:25 ` Atish Patra
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