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AJvYcCV2XnXIZa5hw6uEHlKZGFvdfll2gh2t7v33yiosed6dWWe/hbRYaCuukMfkrFEtXERzcxheSdILnl83U325FL2y5kvRZhkS5CUYMxu/+K+5KQ== X-Gm-Message-State: AOJu0Yx7udKuqeDucM/ApptU02KhTNDCr0NPnW1/FhT6Chu03RPMLfG1 kao7wV5MEDCHnAQBc6ZCZigKX78qrYDEL35P4+6U/y1ObmG9yjnz2NVJG4d7kyc= X-Google-Smtp-Source: AGHT+IHVmqRBo/P6TbzgA+IGRtey54aZ2Ug+NftR1Tt1j04Iczb8JXsSk87BBrBxRg2sWo4RpRMoyA== X-Received: by 2002:a05:6870:40d3:b0:21e:7fba:1960 with SMTP id l19-20020a05687040d300b0021e7fba1960mr1993804oal.18.1708131504258; Fri, 16 Feb 2024 16:58:24 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d188-20020a6336c5000000b005dc89957e06sm487655pga.71.2024.02.16.16.58.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Feb 2024 16:58:23 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Adrian Hunter , Alexander Shishkin , Alexandre Ghiti , Andrew Jones , Anup Patel , Arnaldo Carvalho de Melo , Atish Patra , Christian Brauner , =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Conor Dooley , devicetree@vger.kernel.org, Evan Green , Guo Ren , Heiko Stuebner , Ian Rogers , Ingo Molnar , James Clark , Jing Zhang , Jiri Olsa , Ji Sheng Teoh , John Garry , Jonathan Corbet , Kan Liang , Krzysztof Kozlowski , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, Ley Foon Tan , linux-doc@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Namhyung Kim , Palmer Dabbelt , Paul Walmsley , Peter Zijlstra , Rob Herring , Samuel Holland , Weilin Wang , Will Deacon , kaiwenxue1@gmail.com, Yang Jihong Subject: [PATCH RFC 04/20] dt-bindings: riscv: add Sxcsrind ISA extension description Date: Fri, 16 Feb 2024 16:57:22 -0800 Message-Id: <20240217005738.3744121-5-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240217005738.3744121-1-atishp@rivosinc.com> References: <20240217005738.3744121-1-atishp@rivosinc.com> Precedence: bulk X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add the S[m|s]csrind ISA extension description. Signed-off-by: Atish Patra --- .../devicetree/bindings/riscv/extensions.yaml | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index 63d81dc895e5..77a9f867e36b 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -134,6 +134,20 @@ properties: added by other RISC-V extensions in H/S/VS/U/VU modes and as ratified at commit a28bfae (Ratified (#7)) of riscv-state-enable. + - const: smcsrind + description: | + The standard Smcsrind supervisor-level extension extends the + indirect CSR access mechanism defined by the Smaia extension. This + extension allows other ISA extension to use indirect CSR access + mechanism in M-mode. + + - const: sscsrind + description: | + The standard Sscsrind supervisor-level extension extends the + indirect CSR access mechanism defined by the Ssaia extension. This + extension allows other ISA extension to use indirect CSR access + mechanism in S-mode. + - const: ssaia description: | The standard Ssaia supervisor-level extension for the advanced -- 2.34.1