* [RFC PATCH v2 0/6] TPEBS counting mode support
@ 2024-02-28 16:12 weilin.wang
2024-02-28 16:12 ` [RFC PATCH v2 1/6] perf stat: Parse and find tpebs events when parsing metrics to prepare for perf record sampling weilin.wang
` (5 more replies)
0 siblings, 6 replies; 10+ messages in thread
From: weilin.wang @ 2024-02-28 16:12 UTC (permalink / raw)
To: weilin.wang, Ian Rogers, Peter Zijlstra, Ingo Molnar,
Arnaldo Carvalho de Melo, Alexander Shishkin, Jiri Olsa,
Namhyung Kim, Adrian Hunter, Kan Liang
Cc: linux-perf-users, linux-kernel, Perry Taylor, Samantha Alt,
Caleb Biggers
From: Weilin Wang <weilin.wang@intel.com>
Changes in v2:
- Add MTL metric file
- Add more descriptions and example to the patch [Arnaldo]
Here is an example of running perf stat to collect a metric that uses
retire_latency value of event MEM_INST_RETIRED.STLB_HIT_STORES on a MTL system.
In this simple example, there is no MEM_INST_RETIRED.STLB_HIT_STORES sample.
Therefore, the MEM_INST_RETIRED.STLB_HIT_STORES:p count and retire_latency value
are all 0.
./perf stat -M tma_dtlb_store -a -- sleep 1
[ perf record: Woken up 1 times to write data ]
[ perf record: Captured and wrote 0.000 MB - ]
Performance counter stats for 'system wide':
181,047,168 cpu_core/TOPDOWN.SLOTS/ # 0.6 % tma_dtlb_store
3,195,608 cpu_core/topdown-retiring/
40,156,649 cpu_core/topdown-mem-bound/
3,550,925 cpu_core/topdown-bad-spec/
117,571,818 cpu_core/topdown-fe-bound/
57,118,087 cpu_core/topdown-be-bound/
69,179 cpu_core/EXE_ACTIVITY.BOUND_ON_STORES/
4,582 cpu_core/MEM_INST_RETIRED.STLB_HIT_STORES/
30,183,104 cpu_core/CPU_CLK_UNHALTED.DISTRIBUTED/
30,556,790 cpu_core/CPU_CLK_UNHALTED.THREAD/
168,486 cpu_core/DTLB_STORE_MISSES.WALK_ACTIVE/
0.00 MEM_INST_RETIRED.STLB_HIT_STORES:p 0 0
1.003105924 seconds time elapsed
v1: https://lore.kernel.org/all/20240221072100.412939-1-weilin.wang@intel.com/
Weilin Wang (6):
perf stat: Parse and find tpebs events when parsing metrics to prepare
for perf record sampling
perf stat: Fork and launch perf record when perf stat needs to get
retire latency value for a metric.
perf stat: Add retire latency values into the expr_parse_ctx to
prepare for final metric calculation
perf stat: Create another thread for sample data processing
perf stat: Add retire latency print functions to print out at the very
end of print out
perf vendor events intel: Add MTL metric json files
tools/perf/builtin-stat.c | 222 +-
.../arch/x86/meteorlake/metricgroups.json | 127 +
.../arch/x86/meteorlake/mtl-metrics.json | 2531 +++++++++++++++++
tools/perf/util/data.c | 4 +
tools/perf/util/data.h | 1 +
tools/perf/util/metricgroup.c | 73 +-
tools/perf/util/metricgroup.h | 18 +-
tools/perf/util/stat-display.c | 65 +
tools/perf/util/stat-shadow.c | 18 +
tools/perf/util/stat.h | 5 +
10 files changed, 3046 insertions(+), 18 deletions(-)
create mode 100644 tools/perf/pmu-events/arch/x86/meteorlake/metricgroups.json
create mode 100644 tools/perf/pmu-events/arch/x86/meteorlake/mtl-metrics.json
--
2.43.0
^ permalink raw reply [flat|nested] 10+ messages in thread* [RFC PATCH v2 1/6] perf stat: Parse and find tpebs events when parsing metrics to prepare for perf record sampling 2024-02-28 16:12 [RFC PATCH v2 0/6] TPEBS counting mode support weilin.wang @ 2024-02-28 16:12 ` weilin.wang 2024-02-28 16:12 ` [RFC PATCH v2 2/6] perf stat: Fork and launch perf record when perf stat needs to get retire latency value for a metric weilin.wang ` (4 subsequent siblings) 5 siblings, 0 replies; 10+ messages in thread From: weilin.wang @ 2024-02-28 16:12 UTC (permalink / raw) To: weilin.wang, Ian Rogers, Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo, Alexander Shishkin, Jiri Olsa, Namhyung Kim, Adrian Hunter, Kan Liang Cc: linux-perf-users, linux-kernel, Perry Taylor, Samantha Alt, Caleb Biggers From: Weilin Wang <weilin.wang@intel.com> Metrics that use tpebs values would use the :retire_latency keyword in formulas. We put all these events into a list and pass the list to perf record to collect their retire latency value. Signed-off-by: Weilin Wang <weilin.wang@intel.com> --- tools/perf/builtin-stat.c | 38 +++++++++++++++--- tools/perf/util/metricgroup.c | 73 +++++++++++++++++++++++++++++------ tools/perf/util/metricgroup.h | 10 ++++- tools/perf/util/stat.h | 2 + 4 files changed, 105 insertions(+), 18 deletions(-) diff --git a/tools/perf/builtin-stat.c b/tools/perf/builtin-stat.c index 6bba1a89d030..5a3093541cff 100644 --- a/tools/perf/builtin-stat.c +++ b/tools/perf/builtin-stat.c @@ -162,6 +162,7 @@ static struct perf_stat_config stat_config = { .ctl_fd = -1, .ctl_fd_ack = -1, .iostat_run = false, + .tpebs_event_size = 0, }; static bool cpus_map_matched(struct evsel *a, struct evsel *b) @@ -686,6 +687,12 @@ static enum counter_recovery stat_handle_error(struct evsel *counter) return COUNTER_FATAL; } +static int __run_perf_record(void) +{ + pr_debug("Prepare perf record for retire_latency\n"); + return 0; +} + static int __run_perf_stat(int argc, const char **argv, int run_idx) { int interval = stat_config.interval; @@ -703,6 +710,15 @@ static int __run_perf_stat(int argc, const char **argv, int run_idx) int err; bool second_pass = false; + //Prepare perf record for sampling event retire_latency before fork and prepare workload + if (stat_config.tpebs_event_size > 0) { + int ret; + + ret = __run_perf_record(); + if (ret) + return ret; + } + if (forks) { if (evlist__prepare_workload(evsel_list, &target, argv, is_pipe, workload_exec_failed_signal) < 0) { perror("failed to prepare workload"); @@ -2106,7 +2122,9 @@ static int add_default_attributes(void) stat_config.metric_no_threshold, stat_config.user_requested_cpu_list, stat_config.system_wide, - &stat_config.metric_events); + &stat_config.metric_events, + &stat_config.tpebs_events, + &stat_config.tpebs_event_size); } if (smi_cost) { @@ -2139,7 +2157,9 @@ static int add_default_attributes(void) stat_config.metric_no_threshold, stat_config.user_requested_cpu_list, stat_config.system_wide, - &stat_config.metric_events); + &stat_config.metric_events, + &stat_config.tpebs_events, + &stat_config.tpebs_event_size); } if (topdown_run) { @@ -2173,7 +2193,9 @@ static int add_default_attributes(void) /*metric_no_threshold=*/true, stat_config.user_requested_cpu_list, stat_config.system_wide, - &stat_config.metric_events) < 0) + &stat_config.metric_events, + &stat_config.tpebs_events, + &stat_config.tpebs_event_size) < 0) return -1; } @@ -2214,7 +2236,9 @@ static int add_default_attributes(void) /*metric_no_threshold=*/true, stat_config.user_requested_cpu_list, stat_config.system_wide, - &stat_config.metric_events) < 0) + &stat_config.metric_events, + /*&stat_config.tpebs_events=*/NULL, + /*stat_config.tpebs_event_size=*/0) < 0) return -1; evlist__for_each_entry(metric_evlist, metric_evsel) { @@ -2736,6 +2760,8 @@ int cmd_stat(int argc, const char **argv) } } + INIT_LIST_HEAD(&stat_config.tpebs_events); + /* * Metric parsing needs to be delayed as metrics may optimize events * knowing the target is system-wide. @@ -2748,7 +2774,9 @@ int cmd_stat(int argc, const char **argv) stat_config.metric_no_threshold, stat_config.user_requested_cpu_list, stat_config.system_wide, - &stat_config.metric_events); + &stat_config.metric_events, + &stat_config.tpebs_events, + &stat_config.tpebs_event_size); zfree(&metrics); if (ret) { diff --git a/tools/perf/util/metricgroup.c b/tools/perf/util/metricgroup.c index b24a1c177a80..7a360a9f5b72 100644 --- a/tools/perf/util/metricgroup.c +++ b/tools/perf/util/metricgroup.c @@ -277,7 +277,8 @@ static bool contains_metric_id(struct evsel **metric_events, int num_events, */ static int setup_metric_events(const char *pmu, struct hashmap *ids, struct evlist *metric_evlist, - struct evsel ***out_metric_events) + struct evsel ***out_metric_events, + size_t tpebs_event_size) { struct evsel **metric_events; const char *metric_id; @@ -286,7 +287,7 @@ static int setup_metric_events(const char *pmu, struct hashmap *ids, bool all_pmus = !strcmp(pmu, "all") || perf_pmus__num_core_pmus() == 1 || !is_pmu_core(pmu); *out_metric_events = NULL; - ids_size = hashmap__size(ids); + ids_size = hashmap__size(ids) - tpebs_event_size; metric_events = calloc(ids_size + 1, sizeof(void *)); if (!metric_events) @@ -323,6 +324,7 @@ static int setup_metric_events(const char *pmu, struct hashmap *ids, } } if (matched_events < ids_size) { + pr_debug("Error: matched_events = %lu, ids_size = %lu\n", matched_events, ids_size); free(metric_events); return -EINVAL; } @@ -670,7 +672,9 @@ static int decode_all_metric_ids(struct evlist *perf_evlist, const char *modifie static int metricgroup__build_event_string(struct strbuf *events, const struct expr_parse_ctx *ctx, const char *modifier, - bool group_events) + bool group_events, + struct list_head *tpebs_events __maybe_unused, + size_t *tpebs_event_size) { struct hashmap_entry *cur; size_t bkt; @@ -683,9 +687,42 @@ static int metricgroup__build_event_string(struct strbuf *events, hashmap__for_each_entry(ctx->ids, cur, bkt) { const char *sep, *rsep, *id = cur->pkey; enum perf_tool_event ev; + char *p = strstr(id, ":retire_latency"); pr_debug("found event %s\n", id); + if (p) { + struct tpebs_event *new_event = malloc(sizeof(struct tpebs_event)); + char *name; + char *at; + + pr_debug("event name %s\n", id); + new_event->tpebs_name = strdup(id); + *p = '\0'; + name = malloc(strlen(id) + 2); + if (!name) + return -ENOMEM; + + at = strchr(id, '@'); + if (at != NULL) { + pr_debug("tpebs name %s\n", id); + *at = '/'; + at = strchr(id, '@'); + *at = '/'; + strcpy(name, id); + strcat(name, "p"); + } else { + strcpy(name, id); + strcat(name, ":p"); + } + new_event->name = name; + *tpebs_event_size += 1; + pr_debug("retire_latency required, tpebs_event_size=%lu, new_event=%s\n", + *tpebs_event_size, new_event->name); + list_add_tail(&new_event->nd, tpebs_events); + continue; + } + /* Always move tool events outside of the group. */ ev = perf_tool_event__from_str(id); if (ev != PERF_TOOL_NONE) { @@ -1449,7 +1486,8 @@ static int build_combined_expr_ctx(const struct list_head *metric_list, static int parse_ids(bool metric_no_merge, struct perf_pmu *fake_pmu, struct expr_parse_ctx *ids, const char *modifier, bool group_events, const bool tool_events[PERF_TOOL_MAX], - struct evlist **out_evlist) + struct evlist **out_evlist, struct list_head *tpebs_events, + size_t *tpebs_event_size) { struct parse_events_error parse_error; struct evlist *parsed_evlist; @@ -1492,7 +1530,7 @@ static int parse_ids(bool metric_no_merge, struct perf_pmu *fake_pmu, } } ret = metricgroup__build_event_string(&events, ids, modifier, - group_events); + group_events, tpebs_events, tpebs_event_size); if (ret) return ret; @@ -1531,7 +1569,9 @@ static int parse_groups(struct evlist *perf_evlist, bool system_wide, struct perf_pmu *fake_pmu, struct rblist *metric_events_list, - const struct pmu_metrics_table *table) + const struct pmu_metrics_table *table, + struct list_head *tpebs_events, + size_t *tpebs_event_size) { struct evlist *combined_evlist = NULL; LIST_HEAD(metric_list); @@ -1563,7 +1603,8 @@ static int parse_groups(struct evlist *perf_evlist, /*modifier=*/NULL, /*group_events=*/false, tool_events, - &combined_evlist); + &combined_evlist, + tpebs_events, tpebs_event_size); } if (combined) expr__ctx_free(combined); @@ -1618,14 +1659,15 @@ static int parse_groups(struct evlist *perf_evlist, } if (!metric_evlist) { ret = parse_ids(metric_no_merge, fake_pmu, m->pctx, m->modifier, - m->group_events, tool_events, &m->evlist); + m->group_events, tool_events, &m->evlist, + tpebs_events, tpebs_event_size); if (ret) goto out; metric_evlist = m->evlist; } ret = setup_metric_events(fake_pmu ? "all" : m->pmu, m->pctx->ids, - metric_evlist, &metric_events); + metric_evlist, &metric_events, *tpebs_event_size); if (ret) { pr_err("Cannot resolve IDs for %s: %s\n", m->metric_name, m->metric_expr); @@ -1692,16 +1734,21 @@ int metricgroup__parse_groups(struct evlist *perf_evlist, bool metric_no_threshold, const char *user_requested_cpu_list, bool system_wide, - struct rblist *metric_events) + struct rblist *metric_events, + struct list_head *tpebs_events, + size_t *tpebs_event_size) { const struct pmu_metrics_table *table = pmu_metrics_table__find(); + pr_debug("Test debugging\n"); + if (!table) return -EINVAL; return parse_groups(perf_evlist, pmu, str, metric_no_group, metric_no_merge, metric_no_threshold, user_requested_cpu_list, system_wide, - /*fake_pmu=*/NULL, metric_events, table); + /*fake_pmu=*/NULL, metric_events, table, tpebs_events, + tpebs_event_size); } int metricgroup__parse_groups_test(struct evlist *evlist, @@ -1715,7 +1762,9 @@ int metricgroup__parse_groups_test(struct evlist *evlist, /*metric_no_threshold=*/false, /*user_requested_cpu_list=*/NULL, /*system_wide=*/false, - &perf_pmu__fake, metric_events, table); + &perf_pmu__fake, metric_events, table, + /*tpebs_events=*/NULL, + /*tpebs_event_size=*/0); } struct metricgroup__has_metric_data { diff --git a/tools/perf/util/metricgroup.h b/tools/perf/util/metricgroup.h index d5325c6ec8e1..7c24ed768ff3 100644 --- a/tools/perf/util/metricgroup.h +++ b/tools/perf/util/metricgroup.h @@ -66,6 +66,12 @@ struct metric_expr { int runtime; }; +struct tpebs_event { + struct list_head nd; + const char *name; + const char *tpebs_name; +}; + struct metric_event *metricgroup__lookup(struct rblist *metric_events, struct evsel *evsel, bool create); @@ -77,7 +83,9 @@ int metricgroup__parse_groups(struct evlist *perf_evlist, bool metric_no_threshold, const char *user_requested_cpu_list, bool system_wide, - struct rblist *metric_events); + struct rblist *metric_events, + struct list_head *tpebs_events, + size_t *tpebs_event_size); int metricgroup__parse_groups_test(struct evlist *evlist, const struct pmu_metrics_table *table, const char *str, diff --git a/tools/perf/util/stat.h b/tools/perf/util/stat.h index d6e5c8787ba2..b987960df3c5 100644 --- a/tools/perf/util/stat.h +++ b/tools/perf/util/stat.h @@ -109,6 +109,8 @@ struct perf_stat_config { struct cpu_aggr_map *cpus_aggr_map; u64 *walltime_run; struct rblist metric_events; + struct list_head tpebs_events; + size_t tpebs_event_size; int ctl_fd; int ctl_fd_ack; bool ctl_fd_close; -- 2.43.0 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [RFC PATCH v2 2/6] perf stat: Fork and launch perf record when perf stat needs to get retire latency value for a metric. 2024-02-28 16:12 [RFC PATCH v2 0/6] TPEBS counting mode support weilin.wang 2024-02-28 16:12 ` [RFC PATCH v2 1/6] perf stat: Parse and find tpebs events when parsing metrics to prepare for perf record sampling weilin.wang @ 2024-02-28 16:12 ` weilin.wang 2024-02-28 16:12 ` [RFC PATCH v2 3/6] perf stat: Add retire latency values into the expr_parse_ctx to prepare for final metric calculation weilin.wang ` (3 subsequent siblings) 5 siblings, 0 replies; 10+ messages in thread From: weilin.wang @ 2024-02-28 16:12 UTC (permalink / raw) To: weilin.wang, Ian Rogers, Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo, Alexander Shishkin, Jiri Olsa, Namhyung Kim, Adrian Hunter, Kan Liang Cc: linux-perf-users, linux-kernel, Perry Taylor, Samantha Alt, Caleb Biggers From: Weilin Wang <weilin.wang@intel.com> When retire_latency value is used in a metric formula, perf stat would fork a perf record process with "-e" and "-W" options. Perf record will collect required retire_latency values in parallel while perf stat is collecting counting values. At the point of time that perf stat stops counting, it would send sigterm signal to perf record process and receiving sampling data back from perf record from a pipe. Perf stat will then process the received data to get retire latency data and calculate metric result. Signed-off-by: Weilin Wang <weilin.wang@intel.com> --- tools/perf/builtin-stat.c | 179 +++++++++++++++++++++++++++++++++- tools/perf/util/data.c | 4 + tools/perf/util/data.h | 1 + tools/perf/util/metricgroup.h | 7 ++ tools/perf/util/stat.h | 3 + 5 files changed, 191 insertions(+), 3 deletions(-) diff --git a/tools/perf/builtin-stat.c b/tools/perf/builtin-stat.c index 5a3093541cff..3890a579349e 100644 --- a/tools/perf/builtin-stat.c +++ b/tools/perf/builtin-stat.c @@ -94,8 +94,13 @@ #include <perf/evlist.h> #include <internal/threadmap.h> +#include "util/sample.h" +#include <sys/param.h> +#include <subcmd/run-command.h> + #define DEFAULT_SEPARATOR " " #define FREEZE_ON_SMI_PATH "devices/cpu/freeze_on_smi" +#define PERF_DATA "-" static void print_counters(struct timespec *ts, int argc, const char **argv); @@ -162,7 +167,8 @@ static struct perf_stat_config stat_config = { .ctl_fd = -1, .ctl_fd_ack = -1, .iostat_run = false, - .tpebs_event_size = 0, + .tpebs_event_size = 0, + .tpebs_pid = -1, }; static bool cpus_map_matched(struct evsel *a, struct evsel *b) @@ -687,12 +693,163 @@ static enum counter_recovery stat_handle_error(struct evsel *counter) return COUNTER_FATAL; } -static int __run_perf_record(void) +static int __run_perf_record(const char **record_argv) { + int i = 0; + struct tpebs_event *e; pr_debug("Prepare perf record for retire_latency\n"); + + + record_argv[i++] = "perf"; + record_argv[i++] = "record"; + record_argv[i++] = "-W"; + + if (stat_config.user_requested_cpu_list) { + record_argv[i++] = "-C"; + record_argv[i++] = stat_config.user_requested_cpu_list; + } + + if (stat_config.system_wide) + record_argv[i++] = "-a"; + + list_for_each_entry(e, &stat_config.tpebs_events, nd) { + record_argv[i++] = "-e"; + record_argv[i++] = e->name; + } + + record_argv[i++] = "-o"; + record_argv[i++] = PERF_DATA; + return 0; } +static void prepare_run_command(struct child_process *cmd, + const char **argv) +{ + memset(cmd, 0, sizeof(*cmd)); + cmd->argv = argv; + cmd->out = -1; +} +static int prepare_perf_record(struct child_process *cmd) +{ + const char **record_argv; + + record_argv = calloc(10 + 2 * stat_config.tpebs_event_size, sizeof(char *)); + if (!record_argv) + return -1; + __run_perf_record(record_argv); + + prepare_run_command(cmd, record_argv); + return start_command(cmd); +} + +struct perf_script { + struct perf_tool tool; + struct perf_session *session; + struct evswitch evswitch; + struct perf_cpu_map *cpus; + struct perf_thread_map *threads; + int name_width; +}; + +static void tpebs_data__delete(void) +{ + struct tpebs_retire_lat *r, *rtmp; + struct tpebs_event *e, *etmp; + list_for_each_entry_safe(r, rtmp, &stat_config.tpebs_results, nd) { + list_del_init(&r->nd); + free(r); + } + list_for_each_entry_safe(e, etmp, &stat_config.tpebs_events, nd) { + list_del_init(&e->nd); + free(e); + } +} + +static int process_sample_event(struct perf_tool *tool, + union perf_event *event __maybe_unused, + struct perf_sample *sample, + struct evsel *evsel, + struct machine *machine __maybe_unused) +{ + struct perf_script *script = container_of(tool, struct perf_script, tool); + int ret = 0; + const char *evname; + struct tpebs_retire_lat *t; + + pr_debug("entering function %s\n ", __func__); + evname = evsel__name(evsel); + + pr_debug("[%03d] ", sample->cpu); + pr_debug("%*s: ", script->name_width, evname ?: "[unknown]"); + pr_debug("%16" PRIu16, sample->retire_lat); + pr_debug("\n"); + + // Need to handle per core results? + // We are assuming average retire latency value will be used. Save the number of + // samples and the sum of retire latency value for each event. + list_for_each_entry(t, &stat_config.tpebs_results, nd) { + if (!strcmp(evname, t->name)) { + t->count += 1; + t->sum += sample->retire_lat; + break; + } + } + + return ret; +} + +static int process_feature_event(struct perf_session *session, + union perf_event *event) +{ + if (event->feat.feat_id < HEADER_LAST_FEATURE) + return perf_event__process_feature(session, event); + return 0; +} + +static int __cmd_script(struct child_process *cmd __maybe_unused) +{ + int err = 0; + struct perf_session *session; + struct perf_data data = { + .mode = PERF_DATA_MODE_READ, + .path = PERF_DATA, + .fd = cmd->out, + }; + struct perf_script script = { + .tool = { + .sample = process_sample_event, + .ordered_events = true, + .ordering_requires_timestamps = true, + .feature = process_feature_event, + .attr = perf_event__process_attr, + }, + }; + struct tpebs_event *e; + + list_for_each_entry(e, &stat_config.tpebs_events, nd) { + struct tpebs_retire_lat *new = malloc(sizeof(struct tpebs_retire_lat)); + + if (!new) + return -1; + new->name = strdup(e->name); + new->tpebs_name = strdup(e->tpebs_name); + new->count = 0; + new->sum = 0; + list_add_tail(&new->nd, &stat_config.tpebs_results); + } + + kill(cmd->pid, SIGTERM); + session = perf_session__new(&data, &script.tool); + if (IS_ERR(session)) + return PTR_ERR(session); + script.session = session; + err = perf_session__process_events(session); + perf_session__delete(session); + + return err; +} + static int __run_perf_stat(int argc, const char **argv, int run_idx) { int interval = stat_config.interval; @@ -709,12 +866,14 @@ static int __run_perf_stat(int argc, const char **argv, int run_idx) struct affinity saved_affinity, *affinity = NULL; int err; bool second_pass = false; + struct child_process cmd; //Prepare perf record for sampling event retire_latency before fork and prepare workload if (stat_config.tpebs_event_size > 0) { int ret; - ret = __run_perf_record(); + pr_debug("perf stat pid = %d\n", getpid()); + ret = prepare_perf_record(&cmd); if (ret) return ret; } @@ -924,6 +1083,17 @@ static int __run_perf_stat(int argc, const char **argv, int run_idx) t1 = rdclock(); + if (stat_config.tpebs_event_size > 0) { + int ret; + + pr_debug("pid = %d\n", getpid()); + pr_debug("cmd.pid = %d\n", cmd.pid); + + ret = __cmd_script(&cmd); + close(cmd.out); + pr_debug("%d\n", ret); + } + if (stat_config.walltime_run_table) stat_config.walltime_run[run_idx] = t1 - t0; @@ -2761,6 +2931,7 @@ int cmd_stat(int argc, const char **argv) } INIT_LIST_HEAD(&stat_config.tpebs_events); + INIT_LIST_HEAD(&stat_config.tpebs_results); /* * Metric parsing needs to be delayed as metrics may optimize events @@ -2972,5 +3143,7 @@ int cmd_stat(int argc, const char **argv) metricgroup__rblist_exit(&stat_config.metric_events); evlist__close_control(stat_config.ctl_fd, stat_config.ctl_fd_ack, &stat_config.ctl_fd_close); + tpebs_data__delete(); + return status; } diff --git a/tools/perf/util/data.c b/tools/perf/util/data.c index 08c4bfbd817f..2e2a20fc5c30 100644 --- a/tools/perf/util/data.c +++ b/tools/perf/util/data.c @@ -185,6 +185,10 @@ static bool check_pipe(struct perf_data *data) int fd = perf_data__is_read(data) ? STDIN_FILENO : STDOUT_FILENO; + if (data->fd > 0) { + fd = data->fd; + } + if (!data->path) { if (!fstat(fd, &st) && S_ISFIFO(st.st_mode)) is_pipe = true; diff --git a/tools/perf/util/data.h b/tools/perf/util/data.h index 110f3ebde30f..720638116ca0 100644 --- a/tools/perf/util/data.h +++ b/tools/perf/util/data.h @@ -28,6 +28,7 @@ struct perf_data_file { struct perf_data { const char *path; + int fd; struct perf_data_file file; bool is_pipe; bool is_dir; diff --git a/tools/perf/util/metricgroup.h b/tools/perf/util/metricgroup.h index 7c24ed768ff3..1fa12cc3294e 100644 --- a/tools/perf/util/metricgroup.h +++ b/tools/perf/util/metricgroup.h @@ -71,6 +71,13 @@ struct tpebs_event { const char *name; const char *tpebs_name; }; +struct tpebs_retire_lat { + struct list_head nd; + const char *name; + const char *tpebs_name; + size_t count; + int sum; +}; struct metric_event *metricgroup__lookup(struct rblist *metric_events, struct evsel *evsel, diff --git a/tools/perf/util/stat.h b/tools/perf/util/stat.h index b987960df3c5..2387c6289f93 100644 --- a/tools/perf/util/stat.h +++ b/tools/perf/util/stat.h @@ -111,6 +111,9 @@ struct perf_stat_config { struct rblist metric_events; struct list_head tpebs_events; size_t tpebs_event_size; + struct list_head tpebs_results; + pid_t tpebs_pid; + int tpebs_pipe; int ctl_fd; int ctl_fd_ack; bool ctl_fd_close; -- 2.43.0 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [RFC PATCH v2 3/6] perf stat: Add retire latency values into the expr_parse_ctx to prepare for final metric calculation 2024-02-28 16:12 [RFC PATCH v2 0/6] TPEBS counting mode support weilin.wang 2024-02-28 16:12 ` [RFC PATCH v2 1/6] perf stat: Parse and find tpebs events when parsing metrics to prepare for perf record sampling weilin.wang 2024-02-28 16:12 ` [RFC PATCH v2 2/6] perf stat: Fork and launch perf record when perf stat needs to get retire latency value for a metric weilin.wang @ 2024-02-28 16:12 ` weilin.wang 2024-02-28 16:12 ` [RFC PATCH v2 4/6] perf stat: Create another thread for sample data processing weilin.wang ` (2 subsequent siblings) 5 siblings, 0 replies; 10+ messages in thread From: weilin.wang @ 2024-02-28 16:12 UTC (permalink / raw) To: weilin.wang, Ian Rogers, Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo, Alexander Shishkin, Jiri Olsa, Namhyung Kim, Adrian Hunter, Kan Liang Cc: linux-perf-users, linux-kernel, Perry Taylor, Samantha Alt, Caleb Biggers From: Weilin Wang <weilin.wang@intel.com> Retire latency values of events are used in metric formulas. This update adds code to process data from perf record for required retire latency values. Signed-off-by: Weilin Wang <weilin.wang@intel.com> --- tools/perf/builtin-stat.c | 1 + tools/perf/util/metricgroup.h | 1 + tools/perf/util/stat-shadow.c | 18 ++++++++++++++++++ 3 files changed, 20 insertions(+) diff --git a/tools/perf/builtin-stat.c b/tools/perf/builtin-stat.c index 3890a579349e..3e5865572266 100644 --- a/tools/perf/builtin-stat.c +++ b/tools/perf/builtin-stat.c @@ -792,6 +792,7 @@ static int process_sample_event(struct perf_tool *tool, if (!strcmp(evname, t->name)) { t->count += 1; t->sum += sample->retire_lat; + t->val = t->count > 0 ? t->sum/t->count : 0; break; } } diff --git a/tools/perf/util/metricgroup.h b/tools/perf/util/metricgroup.h index 1fa12cc3294e..08af0f447550 100644 --- a/tools/perf/util/metricgroup.h +++ b/tools/perf/util/metricgroup.h @@ -77,6 +77,7 @@ struct tpebs_retire_lat { const char *tpebs_name; size_t count; int sum; + double val; }; struct metric_event *metricgroup__lookup(struct rblist *metric_events, diff --git a/tools/perf/util/stat-shadow.c b/tools/perf/util/stat-shadow.c index 3466aa952442..c63ba52004fc 100644 --- a/tools/perf/util/stat-shadow.c +++ b/tools/perf/util/stat-shadow.c @@ -355,6 +355,19 @@ static void print_nsecs(struct perf_stat_config *config, print_metric(config, ctxp, NULL, NULL, "CPUs utilized", 0); } +static int prepare_retire_lat(struct expr_parse_ctx *pctx, + struct list_head *retire_lats) +{ + int ret = 0; + struct tpebs_retire_lat *t; + list_for_each_entry(t, retire_lats, nd) { + ret = expr__add_id_val(pctx, strdup(t->tpebs_name), t->val); + if (ret < 0) + return ret; + } + return ret; +} + static int prepare_metric(const struct metric_expr *mexp, const struct evsel *evsel, struct expr_parse_ctx *pctx, @@ -486,6 +499,11 @@ static void generic_metric(struct perf_stat_config *config, pctx->sctx.user_requested_cpu_list = strdup(config->user_requested_cpu_list); pctx->sctx.runtime = runtime; pctx->sctx.system_wide = config->system_wide; + i = prepare_retire_lat(pctx, &config->tpebs_results); + if (i < 0) { + expr__ctx_free(pctx); + return; + } i = prepare_metric(mexp, evsel, pctx, aggr_idx); if (i < 0) { expr__ctx_free(pctx); -- 2.43.0 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [RFC PATCH v2 4/6] perf stat: Create another thread for sample data processing 2024-02-28 16:12 [RFC PATCH v2 0/6] TPEBS counting mode support weilin.wang ` (2 preceding siblings ...) 2024-02-28 16:12 ` [RFC PATCH v2 3/6] perf stat: Add retire latency values into the expr_parse_ctx to prepare for final metric calculation weilin.wang @ 2024-02-28 16:12 ` weilin.wang 2024-02-28 16:12 ` [RFC PATCH v2 5/6] perf stat: Add retire latency print functions to print out at the very end of print out weilin.wang 2024-02-28 16:12 ` [RFC PATCH v2 6/6] perf vendor events intel: Add MTL metric json files weilin.wang 5 siblings, 0 replies; 10+ messages in thread From: weilin.wang @ 2024-02-28 16:12 UTC (permalink / raw) To: weilin.wang, Ian Rogers, Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo, Alexander Shishkin, Jiri Olsa, Namhyung Kim, Adrian Hunter, Kan Liang Cc: linux-perf-users, linux-kernel, Perry Taylor, Samantha Alt, Caleb Biggers From: Weilin Wang <weilin.wang@intel.com> Another thread is required to synchronize between perf stat and perf record when we pass data through pipe. Signed-off-by: Weilin Wang <weilin.wang@intel.com> --- tools/perf/builtin-stat.c | 58 +++++++++++++++++++++++---------------- 1 file changed, 34 insertions(+), 24 deletions(-) diff --git a/tools/perf/builtin-stat.c b/tools/perf/builtin-stat.c index 3e5865572266..2372175d3408 100644 --- a/tools/perf/builtin-stat.c +++ b/tools/perf/builtin-stat.c @@ -777,7 +777,6 @@ static int process_sample_event(struct perf_tool *tool, const char *evname; struct tpebs_retire_lat *t; - pr_debug("entering function %s\n ", __func__); evname = evsel__name(evsel); pr_debug("[%03d] ", sample->cpu); @@ -808,9 +807,9 @@ static int process_feature_event(struct perf_session *session, return 0; } -static int __cmd_script(struct child_process *cmd __maybe_unused) +static void *__cmd_script(void *arg __maybe_unused) { - int err = 0; + struct child_process *cmd = arg; struct perf_session *session; struct perf_data data = { .mode = PERF_DATA_MODE_READ, @@ -826,29 +825,15 @@ static int __cmd_script(struct child_process *cmd __maybe_unused) .attr = perf_event__process_attr, }, }; - struct tpebs_event *e; - - list_for_each_entry(e, &stat_config.tpebs_events, nd) { - struct tpebs_retire_lat *new = malloc(sizeof(struct tpebs_retire_lat)); - - if (!new) - return -1; - new->name = strdup(e->name); - new->tpebs_name = strdup(e->tpebs_name); - new->count = 0; - new->sum = 0; - list_add_tail(&new->nd, &stat_config.tpebs_results); - } - kill(cmd->pid, SIGTERM); session = perf_session__new(&data, &script.tool); if (IS_ERR(session)) - return PTR_ERR(session); + return NULL; script.session = session; - err = perf_session__process_events(session); + perf_session__process_events(session); perf_session__delete(session); - return err; + return NULL; } static int __run_perf_stat(int argc, const char **argv, int run_idx) @@ -868,15 +853,37 @@ static int __run_perf_stat(int argc, const char **argv, int run_idx) int err; bool second_pass = false; struct child_process cmd; + pthread_t thread_script; //Prepare perf record for sampling event retire_latency before fork and prepare workload if (stat_config.tpebs_event_size > 0) { int ret; + struct tpebs_event *e; pr_debug("perf stat pid = %d\n", getpid()); ret = prepare_perf_record(&cmd); if (ret) return ret; + + list_for_each_entry(e, &stat_config.tpebs_events, nd) { + struct tpebs_retire_lat *new = malloc(sizeof(struct tpebs_retire_lat)); + + if (!new) + return -1; + new->name = strdup(e->name); + new->tpebs_name = strdup(e->tpebs_name); + new->count = 0; + new->sum = 0; + list_add_tail(&new->nd, &stat_config.tpebs_results); + } + + if (pthread_create(&thread_script, NULL, __cmd_script, &cmd)) { + kill(cmd.pid, SIGTERM); + close(cmd.out); + pr_err("Could not create thread to process sample data.\n"); + return -1; + } + sleep(2); } if (forks) { @@ -1087,12 +1094,15 @@ static int __run_perf_stat(int argc, const char **argv, int run_idx) if (stat_config.tpebs_event_size > 0) { int ret; - pr_debug("pid = %d\n", getpid()); - pr_debug("cmd.pid = %d\n", cmd.pid); + pr_debug("Workload finished, finishing record\n"); + pr_debug("Perf stat pid = %d, Perf record pid = %d\n", getpid(), cmd.pid); - ret = __cmd_script(&cmd); + kill(cmd.pid, SIGTERM); + pthread_join(thread_script, NULL); close(cmd.out); - pr_debug("%d\n", ret); + ret = finish_command(&cmd); + if (ret != -ERR_RUN_COMMAND_WAITPID_SIGNAL) + return ret; } if (stat_config.walltime_run_table) -- 2.43.0 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [RFC PATCH v2 5/6] perf stat: Add retire latency print functions to print out at the very end of print out 2024-02-28 16:12 [RFC PATCH v2 0/6] TPEBS counting mode support weilin.wang ` (3 preceding siblings ...) 2024-02-28 16:12 ` [RFC PATCH v2 4/6] perf stat: Create another thread for sample data processing weilin.wang @ 2024-02-28 16:12 ` weilin.wang 2024-02-28 16:12 ` [RFC PATCH v2 6/6] perf vendor events intel: Add MTL metric json files weilin.wang 5 siblings, 0 replies; 10+ messages in thread From: weilin.wang @ 2024-02-28 16:12 UTC (permalink / raw) To: weilin.wang, Ian Rogers, Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo, Alexander Shishkin, Jiri Olsa, Namhyung Kim, Adrian Hunter, Kan Liang Cc: linux-perf-users, linux-kernel, Perry Taylor, Samantha Alt, Caleb Biggers From: Weilin Wang <weilin.wang@intel.com> Add print out functions so that users could read retire latency values. Signed-off-by: Weilin Wang <weilin.wang@intel.com> --- tools/perf/util/stat-display.c | 65 ++++++++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/tools/perf/util/stat-display.c b/tools/perf/util/stat-display.c index bfc1d705f437..e2996ba67bfe 100644 --- a/tools/perf/util/stat-display.c +++ b/tools/perf/util/stat-display.c @@ -21,6 +21,7 @@ #include "iostat.h" #include "pmu.h" #include "pmus.h" +#include "metricgroup.h" #define CNTR_NOT_SUPPORTED "<not supported>" #define CNTR_NOT_COUNTED "<not counted>" @@ -34,6 +35,7 @@ #define COMM_LEN 16 #define PID_LEN 7 #define CPUS_LEN 4 +#define RETIRE_LEN 8 static int aggr_header_lens[] = { [AGGR_CORE] = 18, @@ -426,6 +428,67 @@ static void print_metric_std(struct perf_stat_config *config, fprintf(out, " %-*s", METRIC_LEN - n - 1, unit); } +static void print_retire_lat_std(struct perf_stat_config *config, + struct outstate *os) +{ + FILE *out = os->fh; + bool newline = os->newline; + struct tpebs_retire_lat *t; + struct list_head *retire_lats = &config->tpebs_results; + + list_for_each_entry(t, retire_lats, nd) { + if (newline) + do_new_line_std(config, os); + fprintf(out, "%'*.2f %-*s", COUNTS_LEN, t->val, EVNAME_LEN, t->name); + fprintf(out, "%*ld %*d\n", RETIRE_LEN, t->count, + RETIRE_LEN, t->sum); + } +} + +static void print_retire_lat_csv(struct perf_stat_config *config, + struct outstate *os) +{ + FILE *out = os->fh; + struct tpebs_retire_lat *t; + struct list_head *retire_lats = &config->tpebs_results; + const char *sep = config->csv_sep; + + list_for_each_entry(t, retire_lats, nd) { + fprintf(out, "%f%s%s%s%s%ld%s%d\n", t->val, sep, sep, t->name, sep, + t->count, sep, t->sum); + } +} + +static void print_retire_lat_json(struct perf_stat_config *config, + struct outstate *os) +{ + FILE *out = os->fh; + struct tpebs_retire_lat *t; + struct list_head *retire_lats = &config->tpebs_results; + + fprintf(out, "{"); + list_for_each_entry(t, retire_lats, nd) { + fprintf(out, "\"retire_latency-value\" : \"%f\", ", t->val); + fprintf(out, "\"event-name\" : \"%s\"", t->name); + fprintf(out, "\"sample-counts\" : \"%ld\"", t->count); + fprintf(out, "\"retire_latency-sum\" : \"%d\"", t->sum); + } + fprintf(out, "}"); +} + +static void print_retire_lat(struct perf_stat_config *config, + struct outstate *os) +{ + if (!&config->tpebs_results) + return; + if (config->json_output) + print_retire_lat_json(config, os); + else if (config->csv_output) + print_retire_lat_csv(config, os); + else + print_retire_lat_std(config, os); +} + static void new_line_csv(struct perf_stat_config *config, void *ctx) { struct outstate *os = ctx; @@ -1609,6 +1672,8 @@ void evlist__print_counters(struct evlist *evlist, struct perf_stat_config *conf break; } + print_retire_lat(config, &os); + print_footer(config); fflush(config->output); -- 2.43.0 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [RFC PATCH v2 6/6] perf vendor events intel: Add MTL metric json files 2024-02-28 16:12 [RFC PATCH v2 0/6] TPEBS counting mode support weilin.wang ` (4 preceding siblings ...) 2024-02-28 16:12 ` [RFC PATCH v2 5/6] perf stat: Add retire latency print functions to print out at the very end of print out weilin.wang @ 2024-02-28 16:12 ` weilin.wang 2024-02-28 16:50 ` Ian Rogers 5 siblings, 1 reply; 10+ messages in thread From: weilin.wang @ 2024-02-28 16:12 UTC (permalink / raw) To: weilin.wang, Ian Rogers, Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo, Alexander Shishkin, Jiri Olsa, Namhyung Kim, Adrian Hunter, Kan Liang Cc: linux-perf-users, linux-kernel, Perry Taylor, Samantha Alt, Caleb Biggers From: Weilin Wang <weilin.wang@intel.com> Add MTL metric json file at TMA4.7 [1]. Some of the metrics' formulas use TPEBS retire_latency in MTL. [1] https://lore.kernel.org/all/20240214011820.644458-1-irogers@google.com/ Signed-off-by: Weilin Wang <weilin.wang@intel.com> --- .../arch/x86/meteorlake/metricgroups.json | 127 + .../arch/x86/meteorlake/mtl-metrics.json | 2531 +++++++++++++++++ 2 files changed, 2658 insertions(+) create mode 100644 tools/perf/pmu-events/arch/x86/meteorlake/metricgroups.json create mode 100644 tools/perf/pmu-events/arch/x86/meteorlake/mtl-metrics.json diff --git a/tools/perf/pmu-events/arch/x86/meteorlake/metricgroups.json b/tools/perf/pmu-events/arch/x86/meteorlake/metricgroups.json new file mode 100644 index 000000000000..7a03835f262c --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/meteorlake/metricgroups.json @@ -0,0 +1,127 @@ +{ + "Backend": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", + "Bad": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", + "BadSpec": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", + "BigFootprint": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", + "BrMispredicts": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", + "Branches": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", + "C0Wait": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", + "CacheHits": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", + "CodeGen": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", + "Compute": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", + "Cor": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", + "DSB": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", + "DSBmiss": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", + "DataSharing": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", + "Fed": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", + "FetchBW": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", + "FetchLat": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", + "Flops": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", + "FpScalar": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", + "FpVector": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", + "Frontend": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", + "HPC": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", + "IcMiss": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", + "InsType": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", + "IntVector": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", + "L2Evicts": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", + "LSD": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", + "MachineClears": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", + "Machine_Clears": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", + "Mem": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", + "MemOffcore": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", + "MemoryBW": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", + "MemoryBound": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", + "MemoryLat": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", + "MemoryTLB": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", + "Memory_BW": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", + "Memory_Lat": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", + "MicroSeq": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", + "OS": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", + "Offcore": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", + "PGO": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", + "Pipeline": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", + "PortsUtil": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", + "Power": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", + "Prefetches": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", + "Ret": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", + "Retire": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", + "SMT": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", + "Server": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", + "Snoop": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", + "SoC": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", + "Summary": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", + "TmaL1": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", + "TmaL2": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", + "TmaL3mem": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", + "TopdownL1": "Metrics for top-down breakdown at level 1", + "TopdownL2": "Metrics for top-down breakdown at level 2", + "TopdownL3": "Metrics for top-down breakdown at level 3", + "TopdownL4": "Metrics for top-down breakdown at level 4", + "TopdownL5": "Metrics for top-down breakdown at level 5", + "TopdownL6": "Metrics for top-down breakdown at level 6", + "tma_L1_group": "Metrics for top-down breakdown at level 1", + "tma_L2_group": "Metrics for top-down breakdown at level 2", + "tma_L3_group": "Metrics for top-down breakdown at level 3", + "tma_L4_group": "Metrics for top-down breakdown at level 4", + "tma_L5_group": "Metrics for top-down breakdown at level 5", + "tma_L6_group": "Metrics for top-down breakdown at level 6", + "tma_alu_op_utilization_group": "Metrics contributing to tma_alu_op_utilization category", + "tma_assists_group": "Metrics contributing to tma_assists category", + "tma_backend_bound_aux_group": "Metrics contributing to tma_backend_bound_aux category", + "tma_backend_bound_group": "Metrics contributing to tma_backend_bound category", + "tma_bad_speculation_group": "Metrics contributing to tma_bad_speculation category", + "tma_base_group": "Metrics contributing to tma_base category", + "tma_branch_mispredicts_group": "Metrics contributing to tma_branch_mispredicts category", + "tma_branch_resteers_group": "Metrics contributing to tma_branch_resteers category", + "tma_core_bound_group": "Metrics contributing to tma_core_bound category", + "tma_dram_bound_group": "Metrics contributing to tma_dram_bound category", + "tma_dtlb_load_group": "Metrics contributing to tma_dtlb_load category", + "tma_dtlb_store_group": "Metrics contributing to tma_dtlb_store category", + "tma_fetch_bandwidth_group": "Metrics contributing to tma_fetch_bandwidth category", + "tma_fetch_latency_group": "Metrics contributing to tma_fetch_latency category", + "tma_fp_arith_group": "Metrics contributing to tma_fp_arith category", + "tma_fp_vector_group": "Metrics contributing to tma_fp_vector category", + "tma_frontend_bound_group": "Metrics contributing to tma_frontend_bound category", + "tma_heavy_operations_group": "Metrics contributing to tma_heavy_operations category", + "tma_int_operations_group": "Metrics contributing to tma_int_operations category", + "tma_issue2P": "Metrics related by the issue $issue2P", + "tma_issueBM": "Metrics related by the issue $issueBM", + "tma_issueBW": "Metrics related by the issue $issueBW", + "tma_issueComp": "Metrics related by the issue $issueComp", + "tma_issueD0": "Metrics related by the issue $issueD0", + "tma_issueFB": "Metrics related by the issue $issueFB", + "tma_issueFL": "Metrics related by the issue $issueFL", + "tma_issueL1": "Metrics related by the issue $issueL1", + "tma_issueLat": "Metrics related by the issue $issueLat", + "tma_issueMC": "Metrics related by the issue $issueMC", + "tma_issueMS": "Metrics related by the issue $issueMS", + "tma_issueMV": "Metrics related by the issue $issueMV", + "tma_issueRFO": "Metrics related by the issue $issueRFO", + "tma_issueSL": "Metrics related by the issue $issueSL", + "tma_issueSO": "Metrics related by the issue $issueSO", + "tma_issueSmSt": "Metrics related by the issue $issueSmSt", + "tma_issueSpSt": "Metrics related by the issue $issueSpSt", + "tma_issueSyncxn": "Metrics related by the issue $issueSyncxn", + "tma_issueTLB": "Metrics related by the issue $issueTLB", + "tma_l1_bound_group": "Metrics contributing to tma_l1_bound category", + "tma_l3_bound_group": "Metrics contributing to tma_l3_bound category", + "tma_light_operations_group": "Metrics contributing to tma_light_operations category", + "tma_load_op_utilization_group": "Metrics contributing to tma_load_op_utilization category", + "tma_machine_clears_group": "Metrics contributing to tma_machine_clears category", + "tma_mem_latency_group": "Metrics contributing to tma_mem_latency category", + "tma_mem_scheduler_group": "Metrics contributing to tma_mem_scheduler category", + "tma_memory_bound_group": "Metrics contributing to tma_memory_bound category", + "tma_microcode_sequencer_group": "Metrics contributing to tma_microcode_sequencer category", + "tma_mite_group": "Metrics contributing to tma_mite category", + "tma_nuke_group": "Metrics contributing to tma_nuke category", + "tma_other_light_ops_group": "Metrics contributing to tma_other_light_ops category", + "tma_ports_utilization_group": "Metrics contributing to tma_ports_utilization category", + "tma_ports_utilized_0_group": "Metrics contributing to tma_ports_utilized_0 category", + "tma_ports_utilized_3m_group": "Metrics contributing to tma_ports_utilized_3m category", + "tma_resource_bound_group": "Metrics contributing to tma_resource_bound category", + "tma_retiring_group": "Metrics contributing to tma_retiring category", + "tma_serializing_operation_group": "Metrics contributing to tma_serializing_operation category", + "tma_store_bound_group": "Metrics contributing to tma_store_bound category", + "tma_store_op_utilization_group": "Metrics contributing to tma_store_op_utilization category" +} diff --git a/tools/perf/pmu-events/arch/x86/meteorlake/mtl-metrics.json b/tools/perf/pmu-events/arch/x86/meteorlake/mtl-metrics.json new file mode 100644 index 000000000000..12df19538fd6 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/meteorlake/mtl-metrics.json @@ -0,0 +1,2531 @@ +[ + { + "BriefDescription": "C10 residency percent per package", + "MetricExpr": "cstate_pkg@c10\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C10_Pkg_Residency", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "C1 residency percent per core", + "MetricExpr": "cstate_core@c1\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C1_Core_Residency", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "C2 residency percent per package", + "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C2_Pkg_Residency", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "C3 residency percent per package", + "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C3_Pkg_Residency", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "C6 residency percent per core", + "MetricExpr": "cstate_core@c6\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C6_Core_Residency", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "C6 residency percent per package", + "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C6_Pkg_Residency", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "C7 residency percent per core", + "MetricExpr": "cstate_core@c7\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C7_Core_Residency", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "C7 residency percent per package", + "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C7_Pkg_Residency", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "C8 residency percent per package", + "MetricExpr": "cstate_pkg@c8\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C8_Pkg_Residency", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "C9 residency percent per package", + "MetricExpr": "cstate_pkg@c9\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C9_Pkg_Residency", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of cycles spent in System Management Interrupts.", + "MetricExpr": "((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0 else 0)", + "MetricGroup": "smi", + "MetricName": "smi_cycles", + "MetricThreshold": "smi_cycles > 0.1", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Number of SMI interrupts.", + "MetricExpr": "msr@smi@", + "MetricGroup": "smi", + "MetricName": "smi_num", + "ScaleUnit": "1SMI#" + }, + { + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to certain allocation restrictions.", + "MetricExpr": "cpu_atom@TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS@ / tma_info_core_slots", + "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group", + "MetricName": "tma_alloc_restriction", + "MetricThreshold": "tma_alloc_restriction > 0.1", + "ScaleUnit": "100%", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls", + "MetricExpr": "cpu_atom@TOPDOWN_BE_BOUND.ALL@ / tma_info_core_slots", + "MetricGroup": "TopdownL1;tma_L1_group", + "MetricName": "tma_backend_bound", + "MetricThreshold": "tma_backend_bound > 0.1", + "MetricgroupNoGroup": "TopdownL1", + "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls. Note that uops must be available for consumption in order for this event to count. If a uop is not available (IQ is empty), this event will not count. The rest of these subevents count backend stalls, in cycles, due to an outstanding request which is memory bound vs core bound. The subevents are not slot based events and therefore can not be precisely added or subtracted from the Backend_Bound_Aux subevents which are slot based.", + "ScaleUnit": "100%", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls", + "MetricExpr": "tma_backend_bound", + "MetricGroup": "TopdownL1;tma_L1_group", + "MetricName": "tma_backend_bound_aux", + "MetricThreshold": "tma_backend_bound_aux > 0.2", + "MetricgroupNoGroup": "TopdownL1", + "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls. Note that UOPS must be available for consumption in order for this event to count. If a uop is not available (IQ is empty), this event will not count. All of these subevents count backend stalls, in slots, due to a resource limitation. These are not cycle based events and therefore can not be precisely added or subtracted from the Backend_Bound subevents which are cycle based. These subevents are supplementary to Backend_Bound and can be used to analyze results from a resource perspective at allocation.", + "ScaleUnit": "100%", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear", + "MetricExpr": "cpu_atom@TOPDOWN_BAD_SPECULATION.ALL@ / tma_info_core_slots", + "MetricGroup": "TopdownL1;tma_L1_group", + "MetricName": "tma_bad_speculation", + "MetricThreshold": "tma_bad_speculation > 0.15", + "MetricgroupNoGroup": "TopdownL1", + "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ). Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear.", + "ScaleUnit": "100%", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of uops that are not from the microsequencer.", + "MetricExpr": "(cpu_atom@TOPDOWN_RETIRING.ALL@ - cpu_atom@UOPS_RETIRED.MS@) / tma_info_core_slots", + "MetricGroup": "TopdownL2;tma_L2_group;tma_retiring_group", + "MetricName": "tma_base", + "MetricThreshold": "tma_base > 0.6", + "MetricgroupNoGroup": "TopdownL2", + "ScaleUnit": "100%", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend", + "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.BRANCH_DETECT@ / tma_info_core_slots", + "MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_branch_detect", + "MetricThreshold": "tma_branch_detect > 0.05", + "PublicDescription": "Counts the number of issue slots that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.", + "ScaleUnit": "100%", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to branch mispredicts.", + "MetricExpr": "cpu_atom@TOPDOWN_BAD_SPECULATION.MISPREDICT@ / tma_info_core_slots", + "MetricGroup": "TopdownL2;tma_L2_group;tma_bad_speculation_group", + "MetricName": "tma_branch_mispredicts", + "MetricThreshold": "tma_branch_mispredicts > 0.05", + "MetricgroupNoGroup": "TopdownL2", + "ScaleUnit": "100%", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch.", + "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.BRANCH_RESTEER@ / tma_info_core_slots", + "MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_branch_resteer", + "MetricThreshold": "tma_branch_resteer > 0.05", + "ScaleUnit": "100%", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to the microcode sequencer (MS).", + "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.CISC@ / tma_info_core_slots", + "MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", + "MetricName": "tma_cisc", + "MetricThreshold": "tma_cisc > 0.05", + "ScaleUnit": "100%", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of cycles due to backend bound stalls that are core execution bound and not attributed to outstanding demand load or store stalls.", + "MetricExpr": "max(0, tma_backend_bound - tma_memory_bound)", + "MetricGroup": "TopdownL2;tma_L2_group;tma_backend_bound_group", + "MetricName": "tma_core_bound", + "MetricThreshold": "tma_core_bound > 0.1", + "MetricgroupNoGroup": "TopdownL2", + "ScaleUnit": "100%", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to decode stalls.", + "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.DECODE@ / tma_info_core_slots", + "MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", + "MetricName": "tma_decode", + "MetricThreshold": "tma_decode > 0.05", + "ScaleUnit": "100%", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of machine clears relative to the number of nuke slots due to memory disambiguation.", + "MetricExpr": "tma_nuke * (cpu_atom@MACHINE_CLEARS.DISAMBIGUATION@ / cpu_atom@MACHINE_CLEARS.SLOW@)", + "MetricGroup": "TopdownL4;tma_L4_group;tma_nuke_group", + "MetricName": "tma_disambiguation", + "MetricThreshold": "tma_disambiguation > 0.02", + "ScaleUnit": "100%", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (Non-DRAM).", + "MetricExpr": "cpu_atom@MEM_BOUND_STALLS_LOAD.LLC_MISS@ / tma_info_core_clks - max((cpu_atom@MEM_BOUND_STALLS_LOAD.ALL@ - cpu_atom@LD_HEAD.L1_MISS_AT_RET@) / tma_info_core_clks, 0) * cpu_atom@MEM_BOUND_STALLS_LOAD.LLC_MISS@ / cpu_atom@MEM_BOUND_STALLS_LOAD.ALL@", + "MetricGroup": "TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_dram_bound", + "MetricThreshold": "tma_dram_bound > 0.1", + "ScaleUnit": "100%", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to a machine clear classified as a fast nuke due to memory ordering, memory disambiguation and memory renaming.", + "MetricExpr": "cpu_atom@TOPDOWN_BAD_SPECULATION.FASTNUKE@ / tma_info_core_slots", + "MetricGroup": "TopdownL3;tma_L3_group;tma_machine_clears_group", + "MetricName": "tma_fast_nuke", + "MetricThreshold": "tma_fast_nuke > 0.05", + "ScaleUnit": "100%", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations.", + "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH@ / tma_info_core_slots", + "MetricGroup": "TopdownL2;tma_L2_group;tma_frontend_bound_group", + "MetricName": "tma_fetch_bandwidth", + "MetricThreshold": "tma_fetch_bandwidth > 0.1", + "MetricgroupNoGroup": "TopdownL2", + "ScaleUnit": "100%", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations.", + "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.FRONTEND_LATENCY@ / tma_info_core_slots", + "MetricGroup": "TopdownL2;tma_L2_group;tma_frontend_bound_group", + "MetricName": "tma_fetch_latency", + "MetricThreshold": "tma_fetch_latency > 0.15", + "MetricgroupNoGroup": "TopdownL2", + "ScaleUnit": "100%", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of machine clears relative to the number of nuke slots due to FP assists.", + "MetricExpr": "tma_nuke * (cpu_atom@MACHINE_CLEARS.FP_ASSIST@ / cpu_atom@MACHINE_CLEARS.SLOW@)", + "MetricGroup": "TopdownL4;tma_L4_group;tma_nuke_group", + "MetricName": "tma_fp_assist", + "MetricThreshold": "tma_fp_assist > 0.02", + "ScaleUnit": "100%", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of floating point divide operations per uop.", + "MetricExpr": "cpu_atom@UOPS_RETIRED.FPDIV@ / tma_info_core_slots", + "MetricGroup": "TopdownL3;tma_L3_group;tma_base_group", + "MetricName": "tma_fpdiv_uops", + "MetricThreshold": "tma_fpdiv_uops > 0.2", + "ScaleUnit": "100%", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to frontend stalls.", + "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.ALL@ / tma_info_core_slots", + "MetricGroup": "TopdownL1;tma_L1_group", + "MetricName": "tma_frontend_bound", + "MetricThreshold": "tma_frontend_bound > 0.2", + "MetricgroupNoGroup": "TopdownL1", + "ScaleUnit": "100%", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to instruction cache misses.", + "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.ICACHE@ / tma_info_core_slots", + "MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_icache_misses", + "MetricThreshold": "tma_icache_misses > 0.05", + "ScaleUnit": "100%", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "", + "MetricExpr": "cpu_atom@CPU_CLK_UNHALTED.CORE@", + "MetricName": "tma_info_core_clks", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "", + "MetricExpr": "cpu_atom@CPU_CLK_UNHALTED.CORE_P@", + "MetricName": "tma_info_core_clks_p", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Cycles Per Instruction", + "MetricExpr": "tma_info_core_clks / INST_RETIRED.ANY", + "MetricName": "tma_info_core_cpi", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Instructions Per Cycle", + "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / tma_info_core_clks", + "MetricName": "tma_info_core_ipc", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "", + "MetricExpr": "6 * tma_info_core_clks", + "MetricName": "tma_info_core_slots", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Uops Per Instruction", + "MetricExpr": "cpu_atom@UOPS_RETIRED.ALL@ / INST_RETIRED.ANY", + "MetricName": "tma_info_core_upi", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Percent of instruction miss cost that hit in DRAM", + "MetricExpr": "100 * cpu_atom@MEM_BOUND_STALLS_IFETCH.LLC_MISS@ / cpu_atom@MEM_BOUND_STALLS_IFETCH.ALL@", + "MetricName": "tma_info_frontend_inst_miss_cost_dramhit_percent", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Percent of instruction miss cost that hit in the L2", + "MetricExpr": "100 * cpu_atom@MEM_BOUND_STALLS_IFETCH.L2_HIT@ / cpu_atom@MEM_BOUND_STALLS_IFETCH.ALL@", + "MetricName": "tma_info_frontend_inst_miss_cost_l2hit_percent", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Percent of instruction miss cost that hit in the L3", + "MetricExpr": "100 * cpu_atom@MEM_BOUND_STALLS_IFETCH.LLC_HIT@ / cpu_atom@MEM_BOUND_STALLS_IFETCH.ALL@", + "MetricName": "tma_info_frontend_inst_miss_cost_l3hit_percent", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Ratio of all branches which mispredict", + "MetricExpr": "cpu_atom@BR_MISP_RETIRED.ALL_BRANCHES@ / BR_INST_RETIRED.ALL_BRANCHES", + "MetricName": "tma_info_inst_mix_branch_mispredict_ratio", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Ratio between Mispredicted branches and unknown branches", + "MetricExpr": "cpu_atom@BR_MISP_RETIRED.ALL_BRANCHES@ / BACLEARS.ANY", + "MetricName": "tma_info_inst_mix_branch_mispredict_to_unknown_branch_ratio", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Percentage of all uops which are FPDiv uops", + "MetricExpr": "100 * cpu_atom@UOPS_RETIRED.FPDIV@ / UOPS_RETIRED.ALL", + "MetricName": "tma_info_inst_mix_fpdiv_uop_ratio", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Percentage of all uops which are IDiv uops", + "MetricExpr": "100 * cpu_atom@UOPS_RETIRED.IDIV@ / UOPS_RETIRED.ALL", + "MetricName": "tma_info_inst_mix_idiv_uop_ratio", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", + "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / BR_INST_RETIRED.ALL_BRANCHES", + "MetricName": "tma_info_inst_mix_ipbranch", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Instruction per (near) call (lower number means higher occurrence rate)", + "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / BR_INST_RETIRED.NEAR_CALL", + "MetricName": "tma_info_inst_mix_ipcall", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Instructions per Far Branch", + "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / (cpu_atom@BR_INST_RETIRED.FAR_BRANCH@ / 2)", + "MetricName": "tma_info_inst_mix_ipfarbranch", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Instructions per Load", + "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / MEM_UOPS_RETIRED.ALL_LOADS", + "MetricName": "tma_info_inst_mix_ipload", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Instructions per retired conditional Branch Misprediction where the branch was not taken", + "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / (cpu_atom@BR_MISP_RETIRED.COND@ - cpu_atom@BR_MISP_RETIRED.COND_TAKEN@)", + "MetricName": "tma_info_inst_mix_ipmisp_cond_ntaken", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Instructions per retired conditional Branch Misprediction where the branch was taken", + "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / BR_MISP_RETIRED.COND_TAKEN", + "MetricName": "tma_info_inst_mix_ipmisp_cond_taken", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Instructions per retired indirect call or jump Branch Misprediction", + "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / BR_MISP_RETIRED.INDIRECT", + "MetricName": "tma_info_inst_mix_ipmisp_indirect", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Instructions per retired return Branch Misprediction", + "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / BR_MISP_RETIRED.RETURN", + "MetricName": "tma_info_inst_mix_ipmisp_ret", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Instructions per retired Branch Misprediction", + "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricName": "tma_info_inst_mix_ipmispredict", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Instructions per Store", + "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / MEM_UOPS_RETIRED.ALL_STORES", + "MetricName": "tma_info_inst_mix_ipstore", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Percentage of all uops which are ucode ops", + "MetricExpr": "100 * cpu_atom@UOPS_RETIRED.MS@ / UOPS_RETIRED.ALL", + "MetricName": "tma_info_inst_mix_microcode_uop_ratio", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Percentage of all uops which are x87 uops", + "MetricExpr": "100 * cpu_atom@UOPS_RETIRED.X87@ / UOPS_RETIRED.ALL", + "MetricName": "tma_info_inst_mix_x87_uop_ratio", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Percentage of total non-speculative loads with a address aliasing block", + "MetricExpr": "100 * cpu_atom@LD_BLOCKS.ADDRESS_ALIAS@ / MEM_UOPS_RETIRED.ALL_LOADS", + "MetricName": "tma_info_l1_bound_address_alias_blocks", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Percentage of total non-speculative loads that are splits", + "MetricExpr": "100 * cpu_atom@MEM_UOPS_RETIRED.SPLIT_LOADS@ / MEM_UOPS_RETIRED.ALL_LOADS", + "MetricName": "tma_info_l1_bound_load_splits", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Percentage of total non-speculative loads with a store forward or unknown store address block", + "MetricExpr": "100 * cpu_atom@LD_BLOCKS.DATA_UNKNOWN@ / MEM_UOPS_RETIRED.ALL_LOADS", + "MetricName": "tma_info_l1_bound_store_fwd_blocks", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Cycle cost per L2 hit", + "MetricExpr": "cpu_atom@MEM_BOUND_STALLS_LOAD.L2_HIT@ / MEM_LOAD_UOPS_RETIRED.L2_HIT", + "MetricName": "tma_info_memory_cycles_per_demand_load_l2_hit", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Cycle cost per LLC hit", + "MetricExpr": "cpu_atom@MEM_BOUND_STALLS_LOAD.LLC_HIT@ / MEM_LOAD_UOPS_RETIRED.L3_HIT", + "MetricName": "tma_info_memory_cycles_per_demand_load_l3_hit", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "load ops retired per 1000 instruction", + "MetricExpr": "1e3 * cpu_atom@MEM_UOPS_RETIRED.ALL_LOADS@ / INST_RETIRED.ANY", + "MetricName": "tma_info_memory_memloadpki", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Average CPU Utilization", + "MetricExpr": "cpu_atom@CPU_CLK_UNHALTED.REF_TSC@ / TSC", + "MetricName": "tma_info_system_cpu_utilization", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Fraction of cycles spent in Kernel mode", + "MetricExpr": "cpu_atom@CPU_CLK_UNHALTED.CORE@k / CPU_CLK_UNHALTED.CORE", + "MetricGroup": "Summary", + "MetricName": "tma_info_system_kernel_utilization", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Average Frequency Utilization relative nominal frequency", + "MetricExpr": "tma_info_core_clks / CPU_CLK_UNHALTED.REF_TSC", + "MetricGroup": "Power", + "MetricName": "tma_info_system_turbo_utilization", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) misses.", + "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.ITLB_MISS@ / tma_info_core_slots", + "MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_itlb_misses", + "MetricThreshold": "tma_itlb_misses > 0.05", + "ScaleUnit": "100%", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a load block.", + "MetricExpr": "cpu_atom@LD_HEAD.L1_BOUND_AT_RET@ / tma_info_core_clks", + "MetricGroup": "TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_l1_bound", + "MetricThreshold": "tma_l1_bound > 0.1", + "ScaleUnit": "100%", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of cycles a core is stalled due to a demand load which hit in the L2 Cache.", + "MetricExpr": "cpu_atom@MEM_BOUND_STALLS_LOAD.L2_HIT@ / tma_info_core_clks - max((cpu_atom@MEM_BOUND_STALLS_LOAD.ALL@ - cpu_atom@LD_HEAD.L1_MISS_AT_RET@) / tma_info_core_clks, 0) * cpu_atom@MEM_BOUND_STALLS_LOAD.L2_HIT@ / cpu_atom@MEM_BOUND_STALLS_LOAD.ALL@", + "MetricGroup": "TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_l2_bound", + "MetricThreshold": "tma_l2_bound > 0.1", + "ScaleUnit": "100%", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of cycles a core is stalled due to a demand load which hit in the Last Level Cache (LLC) or other core with HITE/F/M.", + "MetricExpr": "cpu_atom@MEM_BOUND_STALLS_LOAD.LLC_HIT@ / tma_info_core_clks - max((cpu_atom@MEM_BOUND_STALLS_LOAD.ALL@ - cpu_atom@LD_HEAD.L1_MISS_AT_RET@) / tma_info_core_clks, 0) * cpu_atom@MEM_BOUND_STALLS_LOAD.LLC_HIT@ / cpu_atom@MEM_BOUND_STALLS_LOAD.ALL@", + "MetricGroup": "TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_l3_bound", + "MetricThreshold": "tma_l3_bound > 0.1", + "ScaleUnit": "100%", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of cycles, relative to the number of mem_scheduler slots, in which uops are blocked due to load buffer full", + "MetricExpr": "tma_mem_scheduler * cpu_atom@MEM_SCHEDULER_BLOCK.LD_BUF@ / MEM_SCHEDULER_BLOCK.ALL", + "MetricGroup": "TopdownL4;tma_L4_group;tma_mem_scheduler_group", + "MetricName": "tma_ld_buffer", + "MetricThreshold": "tma_ld_buffer > 0.05", + "ScaleUnit": "100%", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation.", + "MetricExpr": "cpu_atom@TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS@ / tma_info_core_slots", + "MetricGroup": "TopdownL2;tma_L2_group;tma_bad_speculation_group", + "MetricName": "tma_machine_clears", + "MetricThreshold": "tma_machine_clears > 0.05", + "MetricgroupNoGroup": "TopdownL2", + "ScaleUnit": "100%", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops.", + "MetricExpr": "cpu_atom@TOPDOWN_BE_BOUND.MEM_SCHEDULER@ / tma_info_core_slots", + "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group", + "MetricName": "tma_mem_scheduler", + "MetricThreshold": "tma_mem_scheduler > 0.1", + "ScaleUnit": "100%", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of cycles the core is stalled due to stores or loads.", + "MetricExpr": "min(tma_backend_bound, cpu_atom@LD_HEAD.ANY_AT_RET@ / tma_info_core_clks + tma_store_bound)", + "MetricGroup": "TopdownL2;tma_L2_group;tma_backend_bound_group", + "MetricName": "tma_memory_bound", + "MetricThreshold": "tma_memory_bound > 0.2", + "MetricgroupNoGroup": "TopdownL2", + "ScaleUnit": "100%", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of machine clears relative to the number of nuke slots due to memory ordering.", + "MetricExpr": "tma_nuke * (cpu_atom@MACHINE_CLEARS.MEMORY_ORDERING@ / cpu_atom@MACHINE_CLEARS.SLOW@)", + "MetricGroup": "TopdownL4;tma_L4_group;tma_nuke_group", + "MetricName": "tma_memory_ordering", + "MetricThreshold": "tma_memory_ordering > 0.02", + "ScaleUnit": "100%", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of uops that are from the complex flows issued by the micro-sequencer (MS)", + "MetricExpr": "cpu_atom@UOPS_RETIRED.MS@ / tma_info_core_slots", + "MetricGroup": "TopdownL2;tma_L2_group;tma_retiring_group", + "MetricName": "tma_ms_uops", + "MetricThreshold": "tma_ms_uops > 0.05", + "MetricgroupNoGroup": "TopdownL2", + "PublicDescription": "Counts the number of uops that are from the complex flows issued by the micro-sequencer (MS). This includes uops from flows due to complex instructions, faults, assists, and inserted flows.", + "ScaleUnit": "100%", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops.", + "MetricExpr": "cpu_atom@TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER@ / tma_info_core_slots", + "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group", + "MetricName": "tma_non_mem_scheduler", + "MetricThreshold": "tma_non_mem_scheduler > 0.1", + "ScaleUnit": "100%", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to a machine clear (slow nuke).", + "MetricExpr": "cpu_atom@TOPDOWN_BAD_SPECULATION.NUKE@ / tma_info_core_slots", + "MetricGroup": "TopdownL3;tma_L3_group;tma_machine_clears_group", + "MetricName": "tma_nuke", + "MetricThreshold": "tma_nuke > 0.05", + "ScaleUnit": "100%", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to other common frontend stalls not categorized.", + "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.OTHER@ / tma_info_core_slots", + "MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", + "MetricName": "tma_other_fb", + "MetricThreshold": "tma_other_fb > 0.05", + "ScaleUnit": "100%", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a number of other load blocks.", + "MetricExpr": "cpu_atom@LD_HEAD.OTHER_AT_RET@ / tma_info_core_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_other_l1", + "MetricThreshold": "tma_other_l1 > 0.05", + "ScaleUnit": "100%", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hits in the L2, LLC, DRAM or MMIO (Non-DRAM) but could not be correctly attributed or cycles in which the load miss is waiting on a request buffer.", + "MetricExpr": "max(0, tma_memory_bound - (tma_store_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound))", + "MetricGroup": "TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_other_load_store", + "MetricThreshold": "tma_other_load_store > 0.1", + "ScaleUnit": "100%", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of uops retired excluding ms and fp div uops.", + "MetricExpr": "(cpu_atom@TOPDOWN_RETIRING.ALL@ - cpu_atom@UOPS_RETIRED.MS@ - cpu_atom@UOPS_RETIRED.FPDIV@) / tma_info_core_slots", + "MetricGroup": "TopdownL3;tma_L3_group;tma_base_group", + "MetricName": "tma_other_ret", + "MetricThreshold": "tma_other_ret > 0.3", + "ScaleUnit": "100%", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of machine clears relative to the number of nuke slots due to page faults.", + "MetricExpr": "tma_nuke * (cpu_atom@MACHINE_CLEARS.PAGE_FAULT@ / cpu_atom@MACHINE_CLEARS.SLOW@)", + "MetricGroup": "TopdownL4;tma_L4_group;tma_nuke_group", + "MetricName": "tma_page_fault", + "MetricThreshold": "tma_page_fault > 0.02", + "ScaleUnit": "100%", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to wrong predecodes.", + "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.PREDECODE@ / tma_info_core_slots", + "MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", + "MetricName": "tma_predecode", + "MetricThreshold": "tma_predecode > 0.05", + "ScaleUnit": "100%", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls).", + "MetricExpr": "cpu_atom@TOPDOWN_BE_BOUND.REGISTER@ / tma_info_core_slots", + "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group", + "MetricName": "tma_register", + "MetricThreshold": "tma_register > 0.1", + "ScaleUnit": "100%", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to the reorder buffer being full (ROB stalls).", + "MetricExpr": "cpu_atom@TOPDOWN_BE_BOUND.REORDER_BUFFER@ / tma_info_core_slots", + "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group", + "MetricName": "tma_reorder_buffer", + "MetricThreshold": "tma_reorder_buffer > 0.1", + "ScaleUnit": "100%", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls", + "MetricExpr": "tma_backend_bound", + "MetricGroup": "TopdownL2;tma_L2_group;tma_backend_bound_aux_group", + "MetricName": "tma_resource_bound", + "MetricThreshold": "tma_resource_bound > 0.2", + "MetricgroupNoGroup": "TopdownL2", + "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls. Note that uops must be available for consumption in order for this event to count. If a uop is not available (IQ is empty), this event will not count.", + "ScaleUnit": "100%", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of issue slots that result in retirement slots.", + "MetricExpr": "cpu_atom@TOPDOWN_RETIRING.ALL@ / tma_info_core_slots", + "MetricGroup": "TopdownL1;tma_L1_group", + "MetricName": "tma_retiring", + "MetricThreshold": "tma_retiring > 0.75", + "MetricgroupNoGroup": "TopdownL1", + "ScaleUnit": "100%", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of cycles, relative to the number of mem_scheduler slots, in which uops are blocked due to RSV full relative", + "MetricExpr": "tma_mem_scheduler * cpu_atom@MEM_SCHEDULER_BLOCK.RSV@ / MEM_SCHEDULER_BLOCK.ALL", + "MetricGroup": "TopdownL4;tma_L4_group;tma_mem_scheduler_group", + "MetricName": "tma_rsv", + "MetricThreshold": "tma_rsv > 0.05", + "ScaleUnit": "100%", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS).", + "MetricExpr": "cpu_atom@TOPDOWN_BE_BOUND.SERIALIZATION@ / tma_info_core_slots", + "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group", + "MetricName": "tma_serialization", + "MetricThreshold": "tma_serialization > 0.1", + "ScaleUnit": "100%", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of machine clears relative to the number of nuke slots due to SMC.", + "MetricExpr": "tma_nuke * (cpu_atom@MACHINE_CLEARS.SMC@ / cpu_atom@MACHINE_CLEARS.SLOW@)", + "MetricGroup": "TopdownL4;tma_L4_group;tma_nuke_group", + "MetricName": "tma_smc", + "MetricThreshold": "tma_smc > 0.02", + "ScaleUnit": "100%", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of cycles, relative to the number of mem_scheduler slots, in which uops are blocked due to store buffer full", + "MetricExpr": "tma_store_bound", + "MetricGroup": "TopdownL4;tma_L4_group;tma_mem_scheduler_group", + "MetricName": "tma_st_buffer", + "MetricThreshold": "tma_st_buffer > 0.05", + "ScaleUnit": "100%", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a first level TLB miss.", + "MetricExpr": "cpu_atom@LD_HEAD.DTLB_MISS_AT_RET@ / tma_info_core_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_stlb_hit", + "MetricThreshold": "tma_stlb_hit > 0.05", + "ScaleUnit": "100%", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a second level TLB miss requiring a page walk.", + "MetricExpr": "cpu_atom@LD_HEAD.PGWALK_AT_RET@ / tma_info_core_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_stlb_miss", + "MetricThreshold": "tma_stlb_miss > 0.05", + "ScaleUnit": "100%", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of cycles the core is stalled due to store buffer full.", + "MetricExpr": "tma_mem_scheduler * (cpu_atom@MEM_SCHEDULER_BLOCK.ST_BUF@ / cpu_atom@MEM_SCHEDULER_BLOCK.ALL@)", + "MetricGroup": "TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_store_bound", + "MetricThreshold": "tma_store_bound > 0.1", + "ScaleUnit": "100%", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a store forward block.", + "MetricExpr": "cpu_atom@LD_HEAD.ST_ADDR_AT_RET@ / tma_info_core_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_store_fwd_blk", + "MetricThreshold": "tma_store_fwd_blk > 0.05", + "ScaleUnit": "100%", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Uncore frequency per die [GHZ]", + "MetricExpr": "tma_info_system_socket_clks / #num_dies / duration_time / 1e9", + "MetricGroup": "SoC", + "MetricName": "UNCORE_FREQ", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.", + "MetricExpr": "(cpu_core@UOPS_DISPATCHED.PORT_0@ + cpu_core@UOPS_DISPATCHED.PORT_1@ + cpu_core@UOPS_DISPATCHED.PORT_5_11@ + cpu_core@UOPS_DISPATCHED.PORT_6@) / (5 * tma_info_core_core_clks)", + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", + "MetricName": "tma_alu_op_utilization", + "MetricThreshold": "tma_alu_op_utilization > 0.4", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists", + "MetricExpr": "78 * cpu_core@ASSISTS.ANY@ / tma_info_thread_slots", + "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group", + "MetricName": "tma_assists", + "MetricThreshold": "tma_assists > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1)", + "PublicDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases. Sample with: ASSISTS.ANY", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric estimates fraction of slots the CPU retired uops as a result of handing SSE to AVX* or AVX* to SSE transition Assists.", + "MetricExpr": "63 * cpu_core@ASSISTS.SSE_AVX_MIX@ / tma_info_thread_slots", + "MetricGroup": "HPC;TopdownL5;tma_L5_group;tma_assists_group", + "MetricName": "tma_avx_assists", + "MetricThreshold": "tma_avx_assists > 0.1", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend", + "MetricExpr": "cpu_core@topdown\\-be\\-bound@ / (cpu_core@topdown\\-fe\\-bound@ + cpu_core@topdown\\-bad\\-spec@ + cpu_core@topdown\\-retiring@ + cpu_core@topdown\\-be\\-bound@) + 0 * tma_info_thread_slots", + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_backend_bound", + "MetricThreshold": "tma_backend_bound > 0.2", + "MetricgroupNoGroup": "TopdownL1", + "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. Sample with: TOPDOWN.BACKEND_BOUND_SLOTS", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations", + "MetricExpr": "max(1 - (tma_frontend_bound + tma_backend_bound + tma_retiring), 0)", + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_bad_speculation", + "MetricThreshold": "tma_bad_speculation > 0.15", + "MetricgroupNoGroup": "TopdownL1", + "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction", + "MetricExpr": "cpu_core@topdown\\-br\\-mispredict@ / (cpu_core@topdown\\-fe\\-bound@ + cpu_core@topdown\\-bad\\-spec@ + cpu_core@topdown\\-retiring@ + cpu_core@topdown\\-be\\-bound@) + 0 * tma_info_thread_slots", + "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueBM", + "MetricName": "tma_branch_mispredicts", + "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15", + "MetricgroupNoGroup": "TopdownL2", + "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: TOPDOWN.BR_MISPREDICT_SLOTS. Related metrics: tma_info_bad_spec_branch_misprediction_cost, tma_info_bottleneck_mispredictions, tma_mispredicts_resteers", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers", + "MetricExpr": "cpu_core@INT_MISC.CLEAR_RESTEER_CYCLES@ / tma_info_thread_clks + tma_unknown_branches", + "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_branch_resteers", + "MetricThreshold": "tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings. Sample with: BR_MISP_RETIRED.ALL_BRANCHES", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due staying in C0.1 power-performance optimized state (Faster wakeup time; Smaller power savings).", + "MetricExpr": "cpu_core@CPU_CLK_UNHALTED.C01@ / tma_info_thread_clks", + "MetricGroup": "C0Wait;TopdownL4;tma_L4_group;tma_serializing_operation_group", + "MetricName": "tma_c01_wait", + "MetricThreshold": "tma_c01_wait > 0.05 & (tma_serializing_operation > 0.1 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due staying in C0.2 power-performance optimized state (Slower wakeup time; Larger power savings).", + "MetricExpr": "cpu_core@CPU_CLK_UNHALTED.C02@ / tma_info_thread_clks", + "MetricGroup": "C0Wait;TopdownL4;tma_L4_group;tma_serializing_operation_group", + "MetricName": "tma_c02_wait", + "MetricThreshold": "tma_c02_wait > 0.05 & (tma_serializing_operation > 0.1 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction", + "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)", + "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group", + "MetricName": "tma_cisc", + "MetricThreshold": "tma_cisc > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1)", + "PublicDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources. Sample with: FRONTEND_RETIRED.MS_FLOWS", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears", + "MetricExpr": "(1 - tma_branch_mispredicts / tma_bad_speculation) * cpu_core@INT_MISC.CLEAR_RESTEER_CYCLES@ / tma_info_thread_clks", + "MetricGroup": "BadSpec;MachineClears;TopdownL4;tma_L4_group;tma_branch_resteers_group;tma_issueMC", + "MetricName": "tma_clears_resteers", + "MetricThreshold": "tma_clears_resteers > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES. Related metrics: tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_ms_switches", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses", + "MetricExpr": "(cpu_core@MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS@ * min(cpu_core@MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS@:retire_latency, 24 * tma_info_system_core_frequency) + cpu_core@MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD@ * min(cpu_core@MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD@:retire_latency, 25 * tma_info_system_core_frequency) * (cpu_core@OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM@ / (cpu_core@OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM@ + cpu_core@OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD@))) * (1 + cpu_core@MEM_LOAD_RETIRED.FB_HIT@ / cpu_core@MEM_LOAD_RETIRED.L1_MISS@ / 2) / tma_info_thread_clks", + "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group", + "MetricName": "tma_contested_accesses", + "MetricThreshold": "tma_contested_accesses > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS. Related metrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck", + "MetricExpr": "max(0, tma_backend_bound - tma_memory_bound)", + "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", + "MetricName": "tma_core_bound", + "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2", + "MetricgroupNoGroup": "TopdownL2", + "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses", + "MetricExpr": "(cpu_core@MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD@ * min(cpu_core@MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD@:retire_latency, 24 * tma_info_system_core_frequency) + cpu_core@MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD@ * min(cpu_core@MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD@:retire_latency, 24 * tma_info_system_core_frequency) * (1 - cpu_core@OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM@ / (cpu_core@OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM@ + cpu_core@OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD@))) * (1 + cpu_core@MEM_LOAD_RETIRED.FB_HIT@ / cpu_core@MEM_LOAD_RETIRED.L1_MISS@ / 2) / tma_info_thread_clks", + "MetricGroup": "Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group", + "MetricName": "tma_data_sharing", + "MetricThreshold": "tma_data_sharing > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD. Related metrics: tma_contested_accesses, tma_false_sharing, tma_machine_clears, tma_remote_cache", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric represents fraction of cycles where decoder-0 was the only active decoder", + "MetricExpr": "(cpu_core@INST_DECODED.DECODERS\\,cmask\\=1@ - cpu_core@INST_DECODED.DECODERS\\,cmask\\=2@) / tma_info_core_core_clks / 2", + "MetricGroup": "DSBmiss;FetchBW;TopdownL4;tma_L4_group;tma_issueD0;tma_mite_group", + "MetricName": "tma_decoder0_alone", + "MetricThreshold": "tma_decoder0_alone > 0.1 & (tma_mite > 0.1 & tma_fetch_bandwidth > 0.2)", + "PublicDescription": "This metric represents fraction of cycles where decoder-0 was the only active decoder. Related metrics: tma_few_uops_instructions", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active", + "MetricExpr": "cpu_core@ARITH.DIV_ACTIVE@ / tma_info_thread_clks", + "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group", + "MetricName": "tma_divider", + "MetricThreshold": "tma_divider > 0.2 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDER_UOPS", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads", + "MetricExpr": "cpu_core@MEMORY_ACTIVITY.STALLS_L3_MISS@ / tma_info_thread_clks", + "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_dram_bound", + "MetricThreshold": "tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_MISS_PS", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline", + "MetricExpr": "(cpu_core@IDQ.DSB_CYCLES_ANY@ - cpu_core@IDQ.DSB_CYCLES_OK@) / tma_info_core_core_clks / 2", + "MetricGroup": "DSB;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", + "MetricName": "tma_dsb", + "MetricThreshold": "tma_dsb > 0.15 & tma_fetch_bandwidth > 0.2", + "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines", + "MetricExpr": "cpu_core@DSB2MITE_SWITCHES.PENALTY_CYCLES@ / tma_info_thread_clks", + "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB", + "MetricName": "tma_dsb_switches", + "MetricThreshold": "tma_dsb_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty. Sample with: FRONTEND_RETIRED.DSB_MISS_PS. Related metrics: tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses", + "MetricExpr": "MEM_INST_RETIRED.STLB_HIT_LOADS * min(MEM_INST_RETIRED.STLB_HIT_LOADS:retire_latency, 7) / tma_info_thread_clks + tma_load_stlb_miss", + "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_l1_bound_group", + "MetricName": "tma_dtlb_load", + "MetricThreshold": "tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_INST_RETIRED.STLB_MISS_LOADS_PS. Related metrics: tma_dtlb_store, tma_info_bottleneck_memory_data_tlbs, tma_info_bottleneck_memory_synchronization", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses", + "MetricExpr": "MEM_INST_RETIRED.STLB_HIT_STORES * min(MEM_INST_RETIRED.STLB_HIT_STORES:retire_latency, 7) / tma_info_thread_clks + tma_store_stlb_miss", + "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_store_bound_group", + "MetricName": "tma_dtlb_store", + "MetricThreshold": "tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_INST_RETIRED.STLB_MISS_STORES_PS. Related metrics: tma_dtlb_load, tma_info_bottleneck_memory_data_tlbs, tma_info_bottleneck_memory_synchronization", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing", + "MetricExpr": "28 * tma_info_system_core_frequency * cpu_core@OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM@ / tma_info_thread_clks", + "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_store_bound_group", + "MetricName": "tma_false_sharing", + "MetricThreshold": "tma_false_sharing > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM. Related metrics: tma_contested_accesses, tma_data_sharing, tma_machine_clears, tma_remote_cache", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed", + "MetricExpr": "cpu_core@L1D_PEND_MISS.FB_FULL@ / tma_info_thread_clks", + "MetricGroup": "MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;tma_issueSL;tma_issueSmSt;tma_l1_bound_group", + "MetricName": "tma_fb_full", + "MetricThreshold": "tma_fb_full > 0.3", + "PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory). Related metrics: tma_info_bottleneck_cache_memory_bandwidth, tma_mem_bandwidth, tma_sq_full, tma_store_latency, tma_streaming_stores", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues", + "MetricExpr": "max(0, tma_frontend_bound - tma_fetch_latency)", + "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group;tma_issueFB", + "MetricName": "tma_fetch_bandwidth", + "MetricThreshold": "tma_fetch_bandwidth > 0.2", + "MetricgroupNoGroup": "TopdownL2", + "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Sample with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_switches, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues", + "MetricExpr": "cpu_core@topdown\\-fetch\\-lat@ / (cpu_core@topdown\\-fe\\-bound@ + cpu_core@topdown\\-bad\\-spec@ + cpu_core@topdown\\-retiring@ + cpu_core@topdown\\-be\\-bound@) - cpu_core@INT_MISC.UOP_DROPPING@ / tma_info_thread_slots", + "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group", + "MetricName": "tma_fetch_latency", + "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15", + "MetricgroupNoGroup": "TopdownL2", + "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops", + "MetricExpr": "max(0, tma_heavy_operations - tma_microcode_sequencer)", + "MetricGroup": "TopdownL3;tma_L3_group;tma_heavy_operations_group;tma_issueD0", + "MetricName": "tma_few_uops_instructions", + "MetricThreshold": "tma_few_uops_instructions > 0.05 & tma_heavy_operations > 0.1", + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops. This highly-correlates with the number of uops in such instructions. Related metrics: tma_decoder0_alone", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired)", + "MetricExpr": "tma_x87_use + tma_fp_scalar + tma_fp_vector", + "MetricGroup": "HPC;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_fp_arith", + "MetricThreshold": "tma_fp_arith > 0.2 & tma_light_operations > 0.6", + "PublicDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Floating Point (FP) Assists", + "MetricExpr": "30 * cpu_core@ASSISTS.FP@ / tma_info_thread_slots", + "MetricGroup": "HPC;TopdownL5;tma_L5_group;tma_assists_group", + "MetricName": "tma_fp_assists", + "MetricThreshold": "tma_fp_assists > 0.1", + "PublicDescription": "This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Floating Point (FP) Assists. FP Assist may apply when working with very small floating point values (so-called Denormals).", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired", + "MetricExpr": "cpu_core@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ / (tma_retiring * tma_info_thread_slots)", + "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P", + "MetricName": "tma_fp_scalar", + "MetricThreshold": "tma_fp_scalar > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)", + "PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting. Related metrics: tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths", + "MetricExpr": "cpu_core@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0x3c@ / (tma_retiring * tma_info_thread_slots)", + "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P", + "MetricName": "tma_fp_vector", + "MetricThreshold": "tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)", + "PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors", + "MetricExpr": "(cpu_core@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE@ + cpu_core@FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE@) / (tma_retiring * tma_info_thread_slots)", + "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P", + "MetricName": "tma_fp_vector_128b", + "MetricThreshold": "tma_fp_vector_128b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6))", + "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors", + "MetricExpr": "(cpu_core@FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE@ + cpu_core@FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE@) / (tma_retiring * tma_info_thread_slots)", + "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P", + "MetricName": "tma_fp_vector_256b", + "MetricThreshold": "tma_fp_vector_256b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6))", + "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend", + "MetricExpr": "cpu_core@topdown\\-fe\\-bound@ / (cpu_core@topdown\\-fe\\-bound@ + cpu_core@topdown\\-bad\\-spec@ + cpu_core@topdown\\-retiring@ + cpu_core@topdown\\-be\\-bound@) - cpu_core@INT_MISC.UOP_DROPPING@ / tma_info_thread_slots", + "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_frontend_bound", + "MetricThreshold": "tma_frontend_bound > 0.15", + "MetricgroupNoGroup": "TopdownL1", + "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. Sample with: FRONTEND_RETIRED.LATENCY_GE_4_PS", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions", + "MetricExpr": "tma_light_operations * cpu_core@INST_RETIRED.MACRO_FUSED@ / (tma_retiring * tma_info_thread_slots)", + "MetricGroup": "Branches;Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_fused_instructions", + "MetricThreshold": "tma_fused_instructions > 0.1 & tma_light_operations > 0.6", + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions. CMP+JCC or DEC+JCC are common examples of legacy fusions. {([MTL] Note new MOV+OP and Load+OP fusions appear under Other_Light_Ops in MTL!)}", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences", + "MetricExpr": "cpu_core@topdown\\-heavy\\-ops@ / (cpu_core@topdown\\-fe\\-bound@ + cpu_core@topdown\\-bad\\-spec@ + cpu_core@topdown\\-retiring@ + cpu_core@topdown\\-be\\-bound@) + 0 * tma_info_thread_slots", + "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", + "MetricName": "tma_heavy_operations", + "MetricThreshold": "tma_heavy_operations > 0.1", + "MetricgroupNoGroup": "TopdownL2", + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences. ([ICL+] Note this may overcount due to approximation using indirect events; [ADL+] .). Sample with: UOPS_RETIRED.HEAVY", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses", + "MetricExpr": "cpu_core@ICACHE_DATA.STALLS@ / tma_info_thread_clks", + "MetricGroup": "BigFootprint;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_icache_misses", + "MetricThreshold": "tma_icache_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses. Sample with: FRONTEND_RETIRED.L2_MISS_PS;FRONTEND_RETIRED.L1I_MISS_PS", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)", + "MetricExpr": "tma_info_bottleneck_mispredictions * tma_info_thread_slots / cpu_core@BR_MISP_RETIRED.ALL_BRANCHES@ / 100", + "MetricGroup": "Bad;BrMispredicts;tma_issueBM", + "MetricName": "tma_info_bad_spec_branch_misprediction_cost", + "PublicDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear). Related metrics: tma_branch_mispredicts, tma_info_bottleneck_mispredictions, tma_mispredicts_resteers", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Instructions per retired mispredicts for conditional non-taken branches (lower number means higher occurrence rate).", + "MetricExpr": "cpu_core@INST_RETIRED.ANY@ / BR_MISP_RETIRED.COND_NTAKEN", + "MetricGroup": "Bad;BrMispredicts", + "MetricName": "tma_info_bad_spec_ipmisp_cond_ntaken", + "MetricThreshold": "tma_info_bad_spec_ipmisp_cond_ntaken < 200", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Instructions per retired mispredicts for conditional taken branches (lower number means higher occurrence rate).", + "MetricExpr": "cpu_core@INST_RETIRED.ANY@ / BR_MISP_RETIRED.COND_TAKEN", + "MetricGroup": "Bad;BrMispredicts", + "MetricName": "tma_info_bad_spec_ipmisp_cond_taken", + "MetricThreshold": "tma_info_bad_spec_ipmisp_cond_taken < 200", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Instructions per retired mispredicts for indirect CALL or JMP branches (lower number means higher occurrence rate).", + "MetricExpr": "cpu_core@INST_RETIRED.ANY@ / BR_MISP_RETIRED.INDIRECT", + "MetricGroup": "Bad;BrMispredicts", + "MetricName": "tma_info_bad_spec_ipmisp_indirect", + "MetricThreshold": "tma_info_bad_spec_ipmisp_indirect < 1e3", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Instructions per retired mispredicts for return branches (lower number means higher occurrence rate).", + "MetricExpr": "cpu_core@INST_RETIRED.ANY@ / BR_MISP_RETIRED.RET", + "MetricGroup": "Bad;BrMispredicts", + "MetricName": "tma_info_bad_spec_ipmisp_ret", + "MetricThreshold": "tma_info_bad_spec_ipmisp_ret < 500", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)", + "MetricExpr": "cpu_core@INST_RETIRED.ANY@ / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BadSpec;BrMispredicts", + "MetricName": "tma_info_bad_spec_ipmispredict", + "MetricThreshold": "tma_info_bad_spec_ipmispredict < 200", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Speculative to Retired ratio of all clears (covering mispredicts and nukes)", + "MetricExpr": "cpu_core@INT_MISC.CLEARS_COUNT@ / (cpu_core@BR_MISP_RETIRED.ALL_BRANCHES@ + cpu_core@MACHINE_CLEARS.COUNT@)", + "MetricGroup": "BrMispredicts", + "MetricName": "tma_info_bad_spec_spec_clears_ratio", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts", + "MetricExpr": "(100 * (1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1) if tma_info_system_smt_2t_utilization > 0.5 else 0)", + "MetricGroup": "Cor;SMT", + "MetricName": "tma_info_botlnk_l0_core_bound_likely", + "MetricThreshold": "tma_info_botlnk_l0_core_bound_likely > 0.5", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck", + "MetricExpr": "100 * (tma_fetch_latency * tma_dsb_switches / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_mite / (tma_dsb + tma_lsd + tma_mite))", + "MetricGroup": "DSBmiss;Fed;tma_issueFB", + "MetricName": "tma_info_botlnk_l2_dsb_misses", + "MetricThreshold": "tma_info_botlnk_l2_dsb_misses > 10", + "PublicDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck", + "MetricExpr": "100 * (tma_fetch_latency * tma_icache_misses / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))", + "MetricGroup": "Fed;FetchLat;IcMiss;tma_issueFL", + "MetricName": "tma_info_botlnk_l2_ic_misses", + "MetricThreshold": "tma_info_botlnk_l2_ic_misses > 5", + "PublicDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck. Related metrics: ", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Total pipeline cost of \"useful operations\" - the baseline operations not covered by Branching_Overhead nor Irregular_Overhead.", + "MetricExpr": "100 * (tma_retiring - (cpu_core@BR_INST_RETIRED.ALL_BRANCHES@ + cpu_core@BR_INST_RETIRED.NEAR_CALL@) / tma_info_thread_slots - tma_microcode_sequencer / (tma_few_uops_instructions + tma_microcode_sequencer) * (tma_assists / tma_microcode_sequencer) * tma_heavy_operations)", + "MetricGroup": "Ret", + "MetricName": "tma_info_bottleneck_base_non_br", + "MetricThreshold": "tma_info_bottleneck_base_non_br > 20", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)", + "MetricExpr": "100 * tma_fetch_latency * (tma_itlb_misses + tma_icache_misses + tma_unknown_branches) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)", + "MetricGroup": "BigFootprint;Fed;Frontend;IcMiss;MemoryTLB", + "MetricName": "tma_info_bottleneck_big_code", + "MetricThreshold": "tma_info_bottleneck_big_code > 20", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls)", + "MetricExpr": "100 * ((cpu_core@BR_INST_RETIRED.ALL_BRANCHES@ + cpu_core@BR_INST_RETIRED.NEAR_CALL@) / tma_info_thread_slots)", + "MetricGroup": "Ret", + "MetricName": "tma_info_bottleneck_branching_overhead", + "MetricThreshold": "tma_info_bottleneck_branching_overhead > 5", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Total pipeline cost of external Memory- or Cache-Bandwidth related bottlenecks", + "MetricExpr": "100 * (tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_memory_bound * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_memory_bound * (tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_fb_full / (tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)))", + "MetricGroup": "Mem;MemoryBW;Offcore;tma_issueBW", + "MetricName": "tma_info_bottleneck_cache_memory_bandwidth", + "MetricThreshold": "tma_info_bottleneck_cache_memory_bandwidth > 20", + "PublicDescription": "Total pipeline cost of external Memory- or Cache-Bandwidth related bottlenecks. Related metrics: tma_fb_full, tma_mem_bandwidth, tma_sq_full", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Total pipeline cost of external Memory- or Cache-Latency related bottlenecks", + "MetricExpr": "100 * (tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_memory_bound * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_memory_bound * tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) + tma_memory_bound * (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_store_latency / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores)))", + "MetricGroup": "Mem;MemoryLat;Offcore;tma_issueLat", + "MetricName": "tma_info_bottleneck_cache_memory_latency", + "MetricThreshold": "tma_info_bottleneck_cache_memory_latency > 20", + "PublicDescription": "Total pipeline cost of external Memory- or Cache-Latency related bottlenecks. Related metrics: tma_l3_hit_latency, tma_mem_latency", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Total pipeline cost when the execution is compute-bound - an estimation", + "MetricExpr": "100 * (tma_core_bound * tma_divider / (tma_divider + tma_ports_utilization + tma_serializing_operation) + tma_core_bound * (tma_ports_utilization / (tma_divider + tma_ports_utilization + tma_serializing_operation)) * (tma_ports_utilized_3m / (tma_ports_utilized_0 + tma_ports_utilized_1 + tma_ports_utilized_2 + tma_ports_utilized_3m)))", + "MetricGroup": "Cor;tma_issueComp", + "MetricName": "tma_info_bottleneck_compute_bound_est", + "MetricThreshold": "tma_info_bottleneck_compute_bound_est > 20", + "PublicDescription": "Total pipeline cost when the execution is compute-bound - an estimation. Covers Core Bound when High ILP as well as when long-latency execution units are busy. Related metrics: ", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks", + "MetricExpr": "100 * (tma_frontend_bound - (1 - 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts) * tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) - (1 - cpu_core@INST_RETIRED.REP_ITERATION@ / cpu_core@UOPS_RETIRED.MS\\,cmask\\=1@) * (tma_fetch_latency * (tma_ms_switches + tma_branch_resteers * (tma_clears_resteers + tma_mispredicts_resteers * tma_other_mispredicts / tma_branch_mispredicts) / (tma_clears_resteers + tma_mispredicts_resteers + tma_unknown_branches)) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))) - tma_info_bottleneck_big_code", + "MetricGroup": "Fed;FetchBW;Frontend", + "MetricName": "tma_info_bottleneck_instruction_fetch_bw", + "MetricThreshold": "tma_info_bottleneck_instruction_fetch_bw > 20", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Total pipeline cost of irregular execution (e.g", + "MetricExpr": "100 * ((1 - cpu_core@INST_RETIRED.REP_ITERATION@ / cpu_core@UOPS_RETIRED.MS\\,cmask\\=1@) * (tma_fetch_latency * (tma_ms_switches + tma_branch_resteers * (tma_clears_resteers + tma_mispredicts_resteers * tma_other_mispredicts / tma_branch_mispredicts) / (tma_clears_resteers + tma_mispredicts_resteers + tma_unknown_branches)) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) + 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts * tma_branch_mispredicts + tma_machine_clears * tma_other_nukes / tma_other_nukes + tma_core_bound * (tma_serializing_operation + cpu_core@RS.EMPTY\\,umask\\=1@ / tma_info_thread_clks * tma_ports_utilized_0) / (tma_divider + tma_ports_utilization + tma_serializing_operation) + tma_microcode_sequencer / (tma_few_uops_instructions + tma_microcode_sequencer) * (tma_assists / tma_microcode_sequencer) * tma_heavy_operations)", + "MetricGroup": "Bad;Cor;Ret;tma_issueMS", + "MetricName": "tma_info_bottleneck_irregular_overhead", + "MetricThreshold": "tma_info_bottleneck_irregular_overhead > 10", + "PublicDescription": "Total pipeline cost of irregular execution (e.g. FP-assists in HPC, Wait time with work imbalance multithreaded workloads, overhead in system services or virtualized environments). Related metrics: tma_microcode_sequencer, tma_ms_switches", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)", + "MetricExpr": "100 * (tma_memory_bound * (tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_dtlb_load / (tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_memory_bound * (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores)))", + "MetricGroup": "Mem;MemoryTLB;Offcore;tma_issueTLB", + "MetricName": "tma_info_bottleneck_memory_data_tlbs", + "MetricThreshold": "tma_info_bottleneck_memory_data_tlbs > 20", + "PublicDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs). Related metrics: tma_dtlb_load, tma_dtlb_store, tma_info_bottleneck_memory_synchronization", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Total pipeline cost of Memory Synchronization related bottlenecks (data transfers and coherency updates across processors)", + "MetricExpr": "100 * (tma_memory_bound * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_contested_accesses + tma_data_sharing) / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full) + tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * tma_false_sharing / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores - tma_store_latency)) + tma_machine_clears * (1 - tma_other_nukes / tma_other_nukes))", + "MetricGroup": "Mem;Offcore;tma_issueTLB", + "MetricName": "tma_info_bottleneck_memory_synchronization", + "MetricThreshold": "tma_info_bottleneck_memory_synchronization > 10", + "PublicDescription": "Total pipeline cost of Memory Synchronization related bottlenecks (data transfers and coherency updates across processors). Related metrics: tma_dtlb_load, tma_dtlb_store, tma_info_bottleneck_memory_data_tlbs", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Total pipeline cost of Branch Misprediction related bottlenecks", + "MetricExpr": "100 * (1 - 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts) * (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))", + "MetricGroup": "Bad;BadSpec;BrMispredicts;tma_issueBM", + "MetricName": "tma_info_bottleneck_mispredictions", + "MetricThreshold": "tma_info_bottleneck_mispredictions > 20", + "PublicDescription": "Total pipeline cost of Branch Misprediction related bottlenecks. Related metrics: tma_branch_mispredicts, tma_info_bad_spec_branch_misprediction_cost, tma_mispredicts_resteers", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Total pipeline cost of remaining bottlenecks (apart from those listed in the Info.Bottlenecks metrics class)", + "MetricExpr": "100 - (tma_info_bottleneck_big_code + tma_info_bottleneck_instruction_fetch_bw + tma_info_bottleneck_mispredictions + tma_info_bottleneck_cache_memory_bandwidth + tma_info_bottleneck_cache_memory_latency + tma_info_bottleneck_memory_data_tlbs + tma_info_bottleneck_memory_synchronization + tma_info_bottleneck_compute_bound_est + tma_info_bottleneck_irregular_overhead + tma_info_bottleneck_branching_overhead + tma_info_bottleneck_base_non_br)", + "MetricGroup": "Cor;Offcore", + "MetricName": "tma_info_bottleneck_other_bottlenecks", + "MetricThreshold": "tma_info_bottleneck_other_bottlenecks > 20", + "PublicDescription": "Total pipeline cost of remaining bottlenecks (apart from those listed in the Info.Bottlenecks metrics class). Examples include data-dependencies (Core Bound when Low ILP) and other unlisted memory-related stalls.", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Fraction of branches that are CALL or RET", + "MetricExpr": "(cpu_core@BR_INST_RETIRED.NEAR_CALL@ + cpu_core@BR_INST_RETIRED.NEAR_RETURN@) / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches", + "MetricName": "tma_info_branches_callret", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Fraction of branches that are non-taken conditionals", + "MetricExpr": "cpu_core@BR_INST_RETIRED.COND_NTAKEN@ / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches;CodeGen;PGO", + "MetricName": "tma_info_branches_cond_nt", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Fraction of branches that are taken conditionals", + "MetricExpr": "cpu_core@BR_INST_RETIRED.COND_TAKEN@ / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches;CodeGen;PGO", + "MetricName": "tma_info_branches_cond_tk", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Fraction of branches that are unconditional (direct or indirect) jumps", + "MetricExpr": "(cpu_core@BR_INST_RETIRED.NEAR_TAKEN@ - cpu_core@BR_INST_RETIRED.COND_TAKEN@ - 2 * cpu_core@BR_INST_RETIRED.NEAR_CALL@) / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches", + "MetricName": "tma_info_branches_jump", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Fraction of branches of other types (not individually covered by other metrics in Info.Branches group)", + "MetricExpr": "1 - (tma_info_branches_cond_nt + tma_info_branches_cond_tk + tma_info_branches_callret + tma_info_branches_jump)", + "MetricGroup": "Bad;Branches", + "MetricName": "tma_info_branches_other_branches", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core", + "MetricExpr": "(cpu_core@CPU_CLK_UNHALTED.DISTRIBUTED@ if #SMT_on else tma_info_thread_clks)", + "MetricGroup": "SMT", + "MetricName": "tma_info_core_core_clks", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", + "MetricExpr": "cpu_core@INST_RETIRED.ANY@ / tma_info_core_core_clks", + "MetricGroup": "Ret;SMT;TmaL1;tma_L1_group", + "MetricName": "tma_info_core_coreipc", + "Unit": "cpu_core" + }, + { + "BriefDescription": "uops Executed per Cycle", + "MetricExpr": "cpu_core@UOPS_EXECUTED.THREAD@ / tma_info_thread_clks", + "MetricGroup": "Power", + "MetricName": "tma_info_core_epc", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Floating Point Operations Per Cycle", + "MetricExpr": "(cpu_core@FP_ARITH_INST_RETIRED.SCALAR@ + 2 * cpu_core@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE@ + 4 * cpu_core@FP_ARITH_INST_RETIRED.4_FLOPS@ + 8 * cpu_core@FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE@) / tma_info_core_core_clks", + "MetricGroup": "Flops;Ret", + "MetricName": "tma_info_core_flopc", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)", + "MetricExpr": "(cpu_core@FP_ARITH_DISPATCHED.PORT_0@ + cpu_core@FP_ARITH_DISPATCHED.PORT_1@ + cpu_core@FP_ARITH_DISPATCHED.PORT_5@) / (2 * tma_info_core_core_clks)", + "MetricGroup": "Cor;Flops;HPC", + "MetricName": "tma_info_core_fp_arith_utilization", + "PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common).", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per thread (logical-processor)", + "MetricExpr": "cpu_core@UOPS_EXECUTED.THREAD@ / cpu_core@UOPS_EXECUTED.THREAD\\,cmask\\=1@", + "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", + "MetricName": "tma_info_core_ilp", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", + "MetricExpr": "cpu_core@IDQ.DSB_UOPS@ / cpu_core@UOPS_ISSUED.ANY@", + "MetricGroup": "DSB;Fed;FetchBW;tma_issueFB", + "MetricName": "tma_info_frontend_dsb_coverage", + "MetricThreshold": "tma_info_frontend_dsb_coverage < 0.7 & tma_info_thread_ipc / 6 > 0.35", + "PublicDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_inst_mix_iptb, tma_lcp", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details.", + "MetricExpr": "cpu_core@DSB2MITE_SWITCHES.PENALTY_CYCLES@ / cpu_core@DSB2MITE_SWITCHES.PENALTY_CYCLES\\,cmask\\=1\\,edge@", + "MetricGroup": "DSBmiss", + "MetricName": "tma_info_frontend_dsb_switch_cost", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Average number of Uops issued by front-end when it issued something", + "MetricExpr": "cpu_core@UOPS_ISSUED.ANY@ / cpu_core@UOPS_ISSUED.ANY\\,cmask\\=1@", + "MetricGroup": "Fed;FetchBW", + "MetricName": "tma_info_frontend_fetch_upc", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Average Latency for L1 instruction cache misses", + "MetricExpr": "cpu_core@ICACHE_DATA.STALLS@ / cpu_core@ICACHE_DATA.STALLS\\,cmask\\=1\\,edge@", + "MetricGroup": "Fed;FetchLat;IcMiss", + "MetricName": "tma_info_frontend_icache_miss_latency", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Instructions per non-speculative DSB miss (lower number means higher occurrence rate)", + "MetricExpr": "cpu_core@INST_RETIRED.ANY@ / FRONTEND_RETIRED.ANY_DSB_MISS", + "MetricGroup": "DSBmiss;Fed", + "MetricName": "tma_info_frontend_ipdsb_miss_ret", + "MetricThreshold": "tma_info_frontend_ipdsb_miss_ret < 50", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Instructions per speculative Unknown Branch Misprediction (BAClear) (lower number means higher occurrence rate)", + "MetricExpr": "tma_info_inst_mix_instructions / BACLEARS.ANY", + "MetricGroup": "Fed", + "MetricName": "tma_info_frontend_ipunknown_branch", + "Unit": "cpu_core" + }, + { + "BriefDescription": "L2 cache true code cacheline misses per kilo instruction", + "MetricExpr": "1e3 * cpu_core@FRONTEND_RETIRED.L2_MISS@ / INST_RETIRED.ANY", + "MetricGroup": "IcMiss", + "MetricName": "tma_info_frontend_l2mpki_code", + "Unit": "cpu_core" + }, + { + "BriefDescription": "L2 cache speculative code cacheline misses per kilo instruction", + "MetricExpr": "1e3 * cpu_core@L2_RQSTS.CODE_RD_MISS@ / INST_RETIRED.ANY", + "MetricGroup": "IcMiss", + "MetricName": "tma_info_frontend_l2mpki_code_all", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Fraction of Uops delivered by the LSD (Loop Stream Detector; aka Loop Cache)", + "MetricExpr": "cpu_core@LSD.UOPS@ / cpu_core@UOPS_ISSUED.ANY@", + "MetricGroup": "Fed;LSD", + "MetricName": "tma_info_frontend_lsd_coverage", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Average number of cycles the front-end was delayed due to an Unknown Branch detection", + "MetricExpr": "cpu_core@INT_MISC.UNKNOWN_BRANCH_CYCLES@ / cpu_core@INT_MISC.UNKNOWN_BRANCH_CYCLES\\,cmask\\=1\\,edge@", + "MetricGroup": "Fed", + "MetricName": "tma_info_frontend_unknown_branch_cost", + "PublicDescription": "Average number of cycles the front-end was delayed due to an Unknown Branch detection. See Unknown_Branches node.", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Branch instructions per taken branch.", + "MetricExpr": "cpu_core@BR_INST_RETIRED.ALL_BRANCHES@ / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;PGO", + "MetricName": "tma_info_inst_mix_bptkbranch", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Total number of retired Instructions", + "MetricExpr": "cpu_core@INST_RETIRED.ANY@", + "MetricGroup": "Summary;TmaL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_instructions", + "PublicDescription": "Total number of retired Instructions. Sample with: INST_RETIRED.PREC_DIST", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)", + "MetricExpr": "cpu_core@INST_RETIRED.ANY@ / (cpu_core@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ + cpu_core@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0x3c@)", + "MetricGroup": "Flops;InsType", + "MetricName": "tma_info_inst_mix_iparith", + "MetricThreshold": "tma_info_inst_mix_iparith < 10", + "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting. Approximated prior to BDW.", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate)", + "MetricExpr": "cpu_core@INST_RETIRED.ANY@ / (cpu_core@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE@ + cpu_core@FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE@)", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "tma_info_inst_mix_iparith_avx128", + "MetricThreshold": "tma_info_inst_mix_iparith_avx128 < 10", + "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate)", + "MetricExpr": "cpu_core@INST_RETIRED.ANY@ / (cpu_core@FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE@ + cpu_core@FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE@)", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "tma_info_inst_mix_iparith_avx256", + "MetricThreshold": "tma_info_inst_mix_iparith_avx256 < 10", + "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate)", + "MetricExpr": "cpu_core@INST_RETIRED.ANY@ / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "MetricGroup": "Flops;FpScalar;InsType", + "MetricName": "tma_info_inst_mix_iparith_scalar_dp", + "MetricThreshold": "tma_info_inst_mix_iparith_scalar_dp < 10", + "PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate)", + "MetricExpr": "cpu_core@INST_RETIRED.ANY@ / FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "MetricGroup": "Flops;FpScalar;InsType", + "MetricName": "tma_info_inst_mix_iparith_scalar_sp", + "MetricThreshold": "tma_info_inst_mix_iparith_scalar_sp < 10", + "PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", + "MetricExpr": "cpu_core@INST_RETIRED.ANY@ / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Branches;Fed;InsType", + "MetricName": "tma_info_inst_mix_ipbranch", + "MetricThreshold": "tma_info_inst_mix_ipbranch < 8", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)", + "MetricExpr": "cpu_core@INST_RETIRED.ANY@ / BR_INST_RETIRED.NEAR_CALL", + "MetricGroup": "Branches;Fed;PGO", + "MetricName": "tma_info_inst_mix_ipcall", + "MetricThreshold": "tma_info_inst_mix_ipcall < 200", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)", + "MetricExpr": "cpu_core@INST_RETIRED.ANY@ / (cpu_core@FP_ARITH_INST_RETIRED.SCALAR@ + 2 * cpu_core@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE@ + 4 * cpu_core@FP_ARITH_INST_RETIRED.4_FLOPS@ + 8 * cpu_core@FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE@)", + "MetricGroup": "Flops;InsType", + "MetricName": "tma_info_inst_mix_ipflop", + "MetricThreshold": "tma_info_inst_mix_ipflop < 10", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)", + "MetricExpr": "cpu_core@INST_RETIRED.ANY@ / MEM_INST_RETIRED.ALL_LOADS", + "MetricGroup": "InsType", + "MetricName": "tma_info_inst_mix_ipload", + "MetricThreshold": "tma_info_inst_mix_ipload < 3", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Instructions per PAUSE (lower number means higher occurrence rate)", + "MetricExpr": "tma_info_inst_mix_instructions / CPU_CLK_UNHALTED.PAUSE_INST", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "tma_info_inst_mix_ippause", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)", + "MetricExpr": "cpu_core@INST_RETIRED.ANY@ / MEM_INST_RETIRED.ALL_STORES", + "MetricGroup": "InsType", + "MetricName": "tma_info_inst_mix_ipstore", + "MetricThreshold": "tma_info_inst_mix_ipstore < 8", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrence rate)", + "MetricExpr": "cpu_core@INST_RETIRED.ANY@ / cpu_core@SW_PREFETCH_ACCESS.T0\\,umask\\=0xF@", + "MetricGroup": "Prefetches", + "MetricName": "tma_info_inst_mix_ipswpf", + "MetricThreshold": "tma_info_inst_mix_ipswpf < 100", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "cpu_core@INST_RETIRED.ANY@ / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO;tma_issueFB", + "MetricName": "tma_info_inst_mix_iptb", + "MetricThreshold": "tma_info_inst_mix_iptb < 13", + "PublicDescription": "Instruction per taken branch. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_lcp", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]", + "MetricExpr": "tma_info_memory_l1d_cache_fill_bw", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_memory_core_l1d_cache_fill_bw_2t", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]", + "MetricExpr": "tma_info_memory_l2_cache_fill_bw", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_memory_core_l2_cache_fill_bw_2t", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "tma_info_memory_l3_cache_access_bw", + "MetricGroup": "Mem;MemoryBW;Offcore", + "MetricName": "tma_info_memory_core_l3_cache_access_bw_2t", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "tma_info_memory_l3_cache_fill_bw", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_memory_core_l3_cache_fill_bw_2t", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)", + "MetricExpr": "1e3 * cpu_core@MEM_LOAD_RETIRED.FB_HIT@ / INST_RETIRED.ANY", + "MetricGroup": "CacheHits;Mem", + "MetricName": "tma_info_memory_fb_hpki", + "Unit": "cpu_core" + }, + { + "BriefDescription": "", + "MetricExpr": "64 * cpu_core@L1D.REPLACEMENT@ / 1e9 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_memory_l1d_cache_fill_bw", + "Unit": "cpu_core" + }, + { + "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1e3 * cpu_core@MEM_LOAD_RETIRED.L1_MISS@ / INST_RETIRED.ANY", + "MetricGroup": "CacheHits;Mem", + "MetricName": "tma_info_memory_l1mpki", + "Unit": "cpu_core" + }, + { + "BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1e3 * cpu_core@L2_RQSTS.ALL_DEMAND_DATA_RD@ / INST_RETIRED.ANY", + "MetricGroup": "CacheHits;Mem", + "MetricName": "tma_info_memory_l1mpki_load", + "Unit": "cpu_core" + }, + { + "BriefDescription": "", + "MetricExpr": "64 * cpu_core@L2_LINES_IN.ALL@ / 1e9 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_memory_l2_cache_fill_bw", + "Unit": "cpu_core" + }, + { + "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)", + "MetricExpr": "1e3 * (cpu_core@L2_RQSTS.REFERENCES@ - cpu_core@L2_RQSTS.MISS@) / INST_RETIRED.ANY", + "MetricGroup": "CacheHits;Mem", + "MetricName": "tma_info_memory_l2hpki_all", + "Unit": "cpu_core" + }, + { + "BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1e3 * cpu_core@L2_RQSTS.DEMAND_DATA_RD_HIT@ / INST_RETIRED.ANY", + "MetricGroup": "CacheHits;Mem", + "MetricName": "tma_info_memory_l2hpki_load", + "Unit": "cpu_core" + }, + { + "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1e3 * cpu_core@MEM_LOAD_RETIRED.L2_MISS@ / INST_RETIRED.ANY", + "MetricGroup": "Backend;CacheHits;Mem", + "MetricName": "tma_info_memory_l2mpki", + "Unit": "cpu_core" + }, + { + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)", + "MetricExpr": "1e3 * cpu_core@L2_RQSTS.MISS@ / INST_RETIRED.ANY", + "MetricGroup": "CacheHits;Mem;Offcore", + "MetricName": "tma_info_memory_l2mpki_all", + "Unit": "cpu_core" + }, + { + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1e3 * cpu_core@L2_RQSTS.DEMAND_DATA_RD_MISS@ / INST_RETIRED.ANY", + "MetricGroup": "CacheHits;Mem", + "MetricName": "tma_info_memory_l2mpki_load", + "Unit": "cpu_core" + }, + { + "BriefDescription": "", + "MetricExpr": "64 * cpu_core@OFFCORE_REQUESTS.ALL_REQUESTS@ / 1e9 / duration_time", + "MetricGroup": "Mem;MemoryBW;Offcore", + "MetricName": "tma_info_memory_l3_cache_access_bw", + "Unit": "cpu_core" + }, + { + "BriefDescription": "", + "MetricExpr": "64 * cpu_core@LONGEST_LAT_CACHE.MISS@ / 1e9 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_memory_l3_cache_fill_bw", + "Unit": "cpu_core" + }, + { + "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1e3 * cpu_core@MEM_LOAD_RETIRED.L3_MISS@ / INST_RETIRED.ANY", + "MetricGroup": "Mem", + "MetricName": "tma_info_memory_l3mpki", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Average Parallel L2 cache miss data reads", + "MetricExpr": "cpu_core@OFFCORE_REQUESTS_OUTSTANDING.DATA_RD@ / OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "MetricGroup": "Memory_BW;Offcore", + "MetricName": "tma_info_memory_latency_data_l2_mlp", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Average Latency for L2 cache miss demand Loads", + "MetricExpr": "cpu_core@OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD@ / OFFCORE_REQUESTS.DEMAND_DATA_RD", + "MetricGroup": "Memory_Lat;Offcore", + "MetricName": "tma_info_memory_latency_load_l2_miss_latency", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Average Parallel L2 cache miss demand Loads", + "MetricExpr": "cpu_core@OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD@ / cpu_core@OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD\\,cmask\\=1@", + "MetricGroup": "Memory_BW;Offcore", + "MetricName": "tma_info_memory_latency_load_l2_mlp", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Average Latency for L3 cache miss demand Loads", + "MetricExpr": "cpu_core@OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD@ / OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", + "MetricGroup": "Memory_Lat;Offcore", + "MetricName": "tma_info_memory_latency_load_l3_miss_latency", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)", + "MetricExpr": "cpu_core@L1D_PEND_MISS.PENDING@ / MEM_LOAD_COMPLETED.L1_MISS_ANY", + "MetricGroup": "Mem;MemoryBound;MemoryLat", + "MetricName": "tma_info_memory_load_miss_real_latency", + "Unit": "cpu_core" + }, + { + "BriefDescription": "\"Bus lock\" per kilo instruction", + "MetricExpr": "1e3 * cpu_core@SQ_MISC.BUS_LOCK@ / INST_RETIRED.ANY", + "MetricGroup": "Mem", + "MetricName": "tma_info_memory_mix_bus_lock_pki", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Un-cacheable retired load per kilo instruction", + "MetricExpr": "1e3 * cpu_core@MEM_LOAD_MISC_RETIRED.UC@ / INST_RETIRED.ANY", + "MetricGroup": "Mem", + "MetricName": "tma_info_memory_mix_uc_load_pki", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss", + "MetricExpr": "cpu_core@L1D_PEND_MISS.PENDING@ / L1D_PEND_MISS.PENDING_CYCLES", + "MetricGroup": "Mem;MemoryBW;MemoryBound", + "MetricName": "tma_info_memory_mlp", + "PublicDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)", + "Unit": "cpu_core" + }, + { + "BriefDescription": "STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk)", + "MetricExpr": "1e3 * cpu_core@ITLB_MISSES.WALK_COMPLETED@ / INST_RETIRED.ANY", + "MetricGroup": "Fed;MemoryTLB", + "MetricName": "tma_info_memory_tlb_code_stlb_mpki", + "Unit": "cpu_core" + }, + { + "BriefDescription": "STLB (2nd level TLB) data load speculative misses per kilo instruction (misses of any page-size that complete the page walk)", + "MetricExpr": "1e3 * cpu_core@DTLB_LOAD_MISSES.WALK_COMPLETED@ / INST_RETIRED.ANY", + "MetricGroup": "Mem;MemoryTLB", + "MetricName": "tma_info_memory_tlb_load_stlb_mpki", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", + "MetricExpr": "(cpu_core@ITLB_MISSES.WALK_PENDING@ + cpu_core@DTLB_LOAD_MISSES.WALK_PENDING@ + cpu_core@DTLB_STORE_MISSES.WALK_PENDING@) / (4 * tma_info_core_core_clks)", + "MetricGroup": "Mem;MemoryTLB", + "MetricName": "tma_info_memory_tlb_page_walks_utilization", + "MetricThreshold": "tma_info_memory_tlb_page_walks_utilization > 0.5", + "Unit": "cpu_core" + }, + { + "BriefDescription": "STLB (2nd level TLB) data store speculative misses per kilo instruction (misses of any page-size that complete the page walk)", + "MetricExpr": "1e3 * cpu_core@DTLB_STORE_MISSES.WALK_COMPLETED@ / INST_RETIRED.ANY", + "MetricGroup": "Mem;MemoryTLB", + "MetricName": "tma_info_memory_tlb_store_stlb_mpki", + "Unit": "cpu_core" + }, + { + "BriefDescription": "", + "MetricExpr": "cpu_core@UOPS_EXECUTED.THREAD@ / (cpu_core@UOPS_EXECUTED.CORE_CYCLES_GE_1@ / 2 if #SMT_on else cpu_core@UOPS_EXECUTED.THREAD\\,cmask\\=1@)", + "MetricGroup": "Cor;Pipeline;PortsUtil;SMT", + "MetricName": "tma_info_pipeline_execute", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Instructions per a microcode Assist invocation", + "MetricExpr": "cpu_core@INST_RETIRED.ANY@ / ASSISTS.ANY", + "MetricGroup": "MicroSeq;Pipeline;Ret;Retire", + "MetricName": "tma_info_pipeline_ipassist", + "MetricThreshold": "tma_info_pipeline_ipassist < 100e3", + "PublicDescription": "Instructions per a microcode Assist invocation. See Assists tree node for details (lower number means higher occurrence rate)", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.", + "MetricExpr": "tma_retiring * tma_info_thread_slots / cpu_core@UOPS_RETIRED.SLOTS\\,cmask\\=1@", + "MetricGroup": "Pipeline;Ret", + "MetricName": "tma_info_pipeline_retire", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Estimated fraction of retirement-cycles dealing with repeat instructions", + "MetricExpr": "cpu_core@INST_RETIRED.REP_ITERATION@ / cpu_core@UOPS_RETIRED.SLOTS\\,cmask\\=1@", + "MetricGroup": "MicroSeq;Pipeline;Ret", + "MetricName": "tma_info_pipeline_strings_cycles", + "MetricThreshold": "tma_info_pipeline_strings_cycles > 0.1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Fraction of cycles the processor is waiting yet unhalted; covering legacy PAUSE instruction, as well as C0.1 / C0.2 power-performance optimized states", + "MetricExpr": "cpu_core@CPU_CLK_UNHALTED.C0_WAIT@ / tma_info_thread_clks", + "MetricGroup": "C0Wait", + "MetricName": "tma_info_system_c0_wait", + "MetricThreshold": "tma_info_system_c0_wait > 0.05", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Measured Average Core Frequency for unhalted processors [GHz]", + "MetricExpr": "tma_info_system_turbo_utilization * TSC / 1e9 / duration_time", + "MetricGroup": "Power;Summary", + "MetricName": "tma_info_system_core_frequency", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Average CPU Utilization (percentage)", + "MetricExpr": "cpu_core@CPU_CLK_UNHALTED.REF_TSC@ / TSC", + "MetricGroup": "HPC;Summary", + "MetricName": "tma_info_system_cpu_utilization", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Average number of utilized CPUs", + "MetricExpr": "#num_cpus_online * tma_info_system_cpu_utilization", + "MetricGroup": "Summary", + "MetricName": "tma_info_system_cpus_utilized", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Giga Floating Point Operations Per Second", + "MetricExpr": "(cpu_core@FP_ARITH_INST_RETIRED.SCALAR@ + 2 * cpu_core@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE@ + 4 * cpu_core@FP_ARITH_INST_RETIRED.4_FLOPS@ + 8 * cpu_core@FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE@) / 1e9 / duration_time", + "MetricGroup": "Cor;Flops;HPC", + "MetricName": "tma_info_system_gflops", + "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", + "MetricExpr": "cpu_core@INST_RETIRED.ANY@ / cpu_core@BR_INST_RETIRED.FAR_BRANCH@u", + "MetricGroup": "Branches;OS", + "MetricName": "tma_info_system_ipfarbranch", + "MetricThreshold": "tma_info_system_ipfarbranch < 1e6", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / cpu_core@INST_RETIRED.ANY_P@k", + "MetricGroup": "OS", + "MetricName": "tma_info_system_kernel_cpi", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "OS", + "MetricName": "tma_info_system_kernel_utilization", + "MetricThreshold": "tma_info_system_kernel_utilization > 0.05", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", + "MetricExpr": "(1 - cpu_core@CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE@ / cpu_core@CPU_CLK_UNHALTED.REF_DISTRIBUTED@ if #SMT_on else 0)", + "MetricGroup": "SMT", + "MetricName": "tma_info_system_smt_2t_utilization", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Socket actual clocks when any core is active on that socket", + "MetricExpr": "UNC_CLOCK.SOCKET", + "MetricGroup": "SoC", + "MetricName": "tma_info_system_socket_clks", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Average Frequency Utilization relative nominal frequency", + "MetricExpr": "tma_info_thread_clks / CPU_CLK_UNHALTED.REF_TSC", + "MetricGroup": "Power", + "MetricName": "tma_info_system_turbo_utilization", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", + "MetricExpr": "cpu_core@CPU_CLK_UNHALTED.THREAD@", + "MetricGroup": "Pipeline", + "MetricName": "tma_info_thread_clks", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Cycles Per Instruction (per Logical Processor)", + "MetricExpr": "1 / tma_info_thread_ipc", + "MetricGroup": "Mem;Pipeline", + "MetricName": "tma_info_thread_cpi", + "Unit": "cpu_core" + }, + { + "BriefDescription": "The ratio of Executed- by Issued-Uops", + "MetricExpr": "cpu_core@UOPS_EXECUTED.THREAD@ / UOPS_ISSUED.ANY", + "MetricGroup": "Cor;Pipeline", + "MetricName": "tma_info_thread_execute_per_issue", + "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage.", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Instructions Per Cycle (per Logical Processor)", + "MetricExpr": "cpu_core@INST_RETIRED.ANY@ / tma_info_thread_clks", + "MetricGroup": "Ret;Summary", + "MetricName": "tma_info_thread_ipc", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "cpu_core@TOPDOWN.SLOTS@", + "MetricGroup": "TmaL1;tma_L1_group", + "MetricName": "tma_info_thread_slots", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor", + "MetricExpr": "(tma_info_thread_slots / (cpu_core@TOPDOWN.SLOTS@ / 2) if #SMT_on else 1)", + "MetricGroup": "SMT;TmaL1;tma_L1_group", + "MetricName": "tma_info_thread_slots_utilization", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Uops Per Instruction", + "MetricExpr": "tma_retiring * tma_info_thread_slots / INST_RETIRED.ANY", + "MetricGroup": "Pipeline;Ret;Retire", + "MetricName": "tma_info_thread_uoppi", + "MetricThreshold": "tma_info_thread_uoppi > 1.05", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "tma_retiring * tma_info_thread_slots / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW", + "MetricName": "tma_info_thread_uptb", + "MetricThreshold": "tma_info_thread_uptb < 9", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric represents overall Integer (Int) select operations fraction the CPU has executed (retired)", + "MetricExpr": "tma_int_vector_128b + tma_int_vector_256b", + "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_int_operations", + "MetricThreshold": "tma_int_operations > 0.1 & tma_light_operations > 0.6", + "PublicDescription": "This metric represents overall Integer (Int) select operations fraction the CPU has executed (retired). Vector/Matrix Int operations and shuffles are counted. Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain.", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric represents 128-bit vector Integer ADD/SUB/SAD or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired", + "MetricExpr": "(cpu_core@INT_VEC_RETIRED.ADD_128@ + cpu_core@INT_VEC_RETIRED.VNNI_128@) / (tma_retiring * tma_info_thread_slots)", + "MetricGroup": "Compute;IntVector;Pipeline;TopdownL4;tma_L4_group;tma_int_operations_group;tma_issue2P", + "MetricName": "tma_int_vector_128b", + "MetricThreshold": "tma_int_vector_128b > 0.1 & (tma_int_operations > 0.1 & tma_light_operations > 0.6)", + "PublicDescription": "This metric represents 128-bit vector Integer ADD/SUB/SAD or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric represents 256-bit vector Integer ADD/SUB/SAD/MUL or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired", + "MetricExpr": "(cpu_core@INT_VEC_RETIRED.ADD_256@ + cpu_core@INT_VEC_RETIRED.MUL_256@ + cpu_core@INT_VEC_RETIRED.VNNI_256@) / (tma_retiring * tma_info_thread_slots)", + "MetricGroup": "Compute;IntVector;Pipeline;TopdownL4;tma_L4_group;tma_int_operations_group;tma_issue2P", + "MetricName": "tma_int_vector_256b", + "MetricThreshold": "tma_int_vector_256b > 0.1 & (tma_int_operations > 0.1 & tma_light_operations > 0.6)", + "PublicDescription": "This metric represents 256-bit vector Integer ADD/SUB/SAD/MUL or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses", + "MetricExpr": "cpu_core@ICACHE_TAG.STALLS@ / tma_info_thread_clks", + "MetricGroup": "BigFootprint;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_itlb_misses", + "MetricThreshold": "tma_itlb_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: FRONTEND_RETIRED.STLB_MISS_PS;FRONTEND_RETIRED.ITLB_MISS_PS", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache", + "MetricExpr": "max((cpu_core@EXE_ACTIVITY.BOUND_ON_LOADS@ - cpu_core@MEMORY_ACTIVITY.STALLS_L1D_MISS@) / tma_info_thread_clks, 0)", + "MetricGroup": "CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_issueL1;tma_issueMC;tma_memory_bound_group", + "MetricName": "tma_l1_bound", + "MetricThreshold": "tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache. Sample with: MEM_LOAD_RETIRED.L1_HIT_PS;MEM_LOAD_RETIRED.FB_HIT_PS. Related metrics: tma_clears_resteers, tma_machine_clears, tma_microcode_sequencer, tma_ms_switches, tma_ports_utilized_1", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads", + "MetricExpr": "(cpu_core@MEMORY_ACTIVITY.STALLS_L1D_MISS@ - cpu_core@MEMORY_ACTIVITY.STALLS_L2_MISS@) / tma_info_thread_clks", + "MetricGroup": "CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_l2_bound", + "MetricThreshold": "tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L2_HIT_PS", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core", + "MetricExpr": "(cpu_core@MEMORY_ACTIVITY.STALLS_L2_MISS@ - cpu_core@MEMORY_ACTIVITY.STALLS_L3_MISS@) / tma_info_thread_clks", + "MetricGroup": "CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_l3_bound", + "MetricThreshold": "tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)", + "MetricExpr": "MEM_LOAD_RETIRED.L3_HIT * min(MEM_LOAD_RETIRED.L3_HIT:retire_latency, 9 * tma_info_system_core_frequency) * (1 + cpu_core@MEM_LOAD_RETIRED.FB_HIT@ / cpu_core@MEM_LOAD_RETIRED.L1_MISS@ / 2) / tma_info_thread_clks", + "MetricGroup": "MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_l3_bound_group", + "MetricName": "tma_l3_hit_latency", + "MetricThreshold": "tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS. Related metrics: tma_info_bottleneck_cache_memory_latency, tma_mem_latency", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs)", + "MetricExpr": "cpu_core@DECODE.LCP@ / tma_info_thread_clks", + "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB", + "MetricName": "tma_lcp", + "MetricThreshold": "tma_lcp > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation)", + "MetricExpr": "max(0, tma_retiring - tma_heavy_operations)", + "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", + "MetricName": "tma_light_operations", + "MetricThreshold": "tma_light_operations > 0.6", + "MetricgroupNoGroup": "TopdownL2", + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized code running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. ([ICL+] Note this may undercount due to approximation using indirect events; [ADL+] .). Sample with: INST_RETIRED.PREC_DIST", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations", + "MetricExpr": "cpu_core@UOPS_DISPATCHED.PORT_2_3_10@ / (3 * tma_info_core_core_clks)", + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", + "MetricName": "tma_load_op_utilization", + "MetricThreshold": "tma_load_op_utilization > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations. Sample with: UOPS_DISPATCHED.PORT_2_3_10", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric roughly estimates the fraction of cycles where the (first level) DTLB was missed by load accesses, that later on hit in second-level TLB (STLB)", + "MetricExpr": "max(0, tma_dtlb_load - tma_load_stlb_miss)", + "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_load_group", + "MetricName": "tma_load_stlb_hit", + "MetricThreshold": "tma_load_stlb_hit > 0.05 & (tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric estimates the fraction of cycles where the Second-level TLB (STLB) was missed by load accesses, performing a hardware page walk", + "MetricExpr": "cpu_core@DTLB_LOAD_MISSES.WALK_ACTIVE@ / tma_info_thread_clks", + "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_load_group", + "MetricName": "tma_load_stlb_miss", + "MetricThreshold": "tma_load_stlb_miss > 0.05 & (tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations", + "MetricExpr": "MEM_INST_RETIRED.LOCK_LOADS * MEM_INST_RETIRED.LOCK_LOADS:retire_latency / tma_info_thread_clks", + "MetricGroup": "Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_l1_bound_group", + "MetricName": "tma_lock_latency", + "MetricThreshold": "tma_lock_latency > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOADS_PS. Related metrics: tma_store_latency", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to LSD (Loop Stream Detector) unit", + "MetricExpr": "(cpu_core@LSD.CYCLES_ACTIVE@ - cpu_core@LSD.CYCLES_OK@) / tma_info_core_core_clks / 2", + "MetricGroup": "FetchBW;LSD;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", + "MetricName": "tma_lsd", + "MetricThreshold": "tma_lsd > 0.15 & tma_fetch_bandwidth > 0.2", + "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to LSD (Loop Stream Detector) unit. LSD typically does well sustaining Uop supply. However; in some rare cases; optimal uop-delivery could not be reached for small loops whose size (in terms of number of uops) does not suit well the LSD structure.", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears", + "MetricExpr": "max(0, tma_bad_speculation - tma_branch_mispredicts)", + "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", + "MetricName": "tma_machine_clears", + "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation > 0.15", + "MetricgroupNoGroup": "TopdownL2", + "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_cache", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM)", + "MetricExpr": "min(cpu_core@CPU_CLK_UNHALTED.THREAD@, cpu_core@OFFCORE_REQUESTS_OUTSTANDING.DATA_RD\\,cmask\\=4@) / tma_info_thread_clks", + "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueBW", + "MetricName": "tma_mem_bandwidth", + "MetricThreshold": "tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that). Related metrics: tma_fb_full, tma_info_bottleneck_cache_memory_bandwidth, tma_sq_full", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM)", + "MetricExpr": "min(cpu_core@CPU_CLK_UNHALTED.THREAD@, cpu_core@OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD@) / tma_info_thread_clks - tma_mem_bandwidth", + "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueLat", + "MetricName": "tma_mem_latency", + "MetricThreshold": "tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that). Related metrics: tma_info_bottleneck_cache_memory_latency, tma_l3_hit_latency", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck", + "MetricExpr": "cpu_core@topdown\\-mem\\-bound@ / (cpu_core@topdown\\-fe\\-bound@ + cpu_core@topdown\\-bad\\-spec@ + cpu_core@topdown\\-retiring@ + cpu_core@topdown\\-be\\-bound@) + 0 * tma_info_thread_slots", + "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", + "MetricName": "tma_memory_bound", + "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0.2", + "MetricgroupNoGroup": "TopdownL2", + "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to LFENCE Instructions.", + "MetricConstraint": "NO_GROUP_EVENTS_NMI", + "MetricExpr": "13 * cpu_core@MISC2_RETIRED.LFENCE@ / tma_info_thread_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_serializing_operation_group", + "MetricName": "tma_memory_fence", + "MetricThreshold": "tma_memory_fence > 0.05 & (tma_serializing_operation > 0.1 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring memory operations -- uops for memory load or store accesses.", + "MetricExpr": "tma_light_operations * cpu_core@MEM_UOP_RETIRED.ANY@ / (tma_retiring * tma_info_thread_slots)", + "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_memory_operations", + "MetricThreshold": "tma_memory_operations > 0.1 & tma_light_operations > 0.6", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit", + "MetricExpr": "cpu_core@UOPS_RETIRED.MS@ / tma_info_thread_slots", + "MetricGroup": "MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group;tma_issueMC;tma_issueMS", + "MetricName": "tma_microcode_sequencer", + "MetricThreshold": "tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1", + "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: UOPS_RETIRED.MS. Related metrics: tma_clears_resteers, tma_info_bottleneck_irregular_overhead, tma_l1_bound, tma_machine_clears, tma_ms_switches", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage", + "MetricExpr": "tma_branch_mispredicts / tma_bad_speculation * cpu_core@INT_MISC.CLEAR_RESTEER_CYCLES@ / tma_info_thread_clks", + "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_L4_group;tma_branch_resteers_group;tma_issueBM", + "MetricName": "tma_mispredicts_resteers", + "MetricThreshold": "tma_mispredicts_resteers > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES. Related metrics: tma_branch_mispredicts, tma_info_bad_spec_branch_misprediction_cost, tma_info_bottleneck_mispredictions", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline)", + "MetricExpr": "(cpu_core@IDQ.MITE_CYCLES_ANY@ - cpu_core@IDQ.MITE_CYCLES_OK@) / tma_info_core_core_clks / 2", + "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", + "MetricName": "tma_mite", + "MetricThreshold": "tma_mite > 0.1 & tma_fetch_bandwidth > 0.2", + "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck. Sample with: FRONTEND_RETIRED.ANY_DSB_MISS", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric estimates penalty in terms of percentage of([SKL+] injected blend uops out of all Uops Issued -- the Count Domain; [ADL+] cycles)", + "MetricExpr": "160 * cpu_core@ASSISTS.SSE_AVX_MIX@ / tma_info_thread_clks", + "MetricGroup": "TopdownL5;tma_L5_group;tma_issueMV;tma_ports_utilized_0_group", + "MetricName": "tma_mixing_vectors", + "MetricThreshold": "tma_mixing_vectors > 0.05", + "PublicDescription": "This metric estimates penalty in terms of percentage of([SKL+] injected blend uops out of all Uops Issued -- the Count Domain; [ADL+] cycles). Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic. Related metrics: tma_ms_switches", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS)", + "MetricExpr": "3 * cpu_core@UOPS_RETIRED.MS\\,cmask\\=1\\,edge@ / (cpu_core@UOPS_RETIRED.SLOTS@ / cpu_core@UOPS_ISSUED.ANY@) / tma_info_thread_clks", + "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueMC;tma_issueMS;tma_issueMV;tma_issueSO", + "MetricName": "tma_ms_switches", + "MetricThreshold": "tma_ms_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals. Sample with: FRONTEND_RETIRED.MS_FLOWS. Related metrics: tma_clears_resteers, tma_info_bottleneck_irregular_overhead, tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_mixing_vectors, tma_serializing_operation", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused", + "MetricExpr": "tma_light_operations * (cpu_core@BR_INST_RETIRED.ALL_BRANCHES@ - cpu_core@INST_RETIRED.MACRO_FUSED@) / (tma_retiring * tma_info_thread_slots)", + "MetricGroup": "Branches;Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_non_fused_branches", + "MetricThreshold": "tma_non_fused_branches > 0.1 & tma_light_operations > 0.6", + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused. Non-conditional branches like direct JMP or CALL would count here. Can be used to examine fusible conditional jumps that were not fused.", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions", + "MetricExpr": "tma_light_operations * cpu_core@INST_RETIRED.NOP@ / (tma_retiring * tma_info_thread_slots)", + "MetricGroup": "Pipeline;TopdownL4;tma_L4_group;tma_other_light_ops_group", + "MetricName": "tma_nop_instructions", + "MetricThreshold": "tma_nop_instructions > 0.1 & (tma_other_light_ops > 0.3 & tma_light_operations > 0.6)", + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body. Sample with: INST_RETIRED.NOP", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes", + "MetricExpr": "max(0, tma_light_operations - (tma_fp_arith + tma_int_operations + tma_memory_operations + tma_fused_instructions + tma_non_fused_branches))", + "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_other_light_ops", + "MetricThreshold": "tma_other_light_ops > 0.3 & tma_light_operations > 0.6", + "PublicDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric estimates fraction of slots the CPU was stalled due to other cases of misprediction (non-retired x86 branches or other types).", + "MetricExpr": "max(tma_branch_mispredicts * (1 - cpu_core@BR_MISP_RETIRED.ALL_BRANCHES@ / (cpu_core@INT_MISC.CLEARS_COUNT@ - cpu_core@MACHINE_CLEARS.COUNT@)), 0.0001)", + "MetricGroup": "BrMispredicts;TopdownL3;tma_L3_group;tma_branch_mispredicts_group", + "MetricName": "tma_other_mispredicts", + "MetricThreshold": "tma_other_mispredicts > 0.05 & (tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15)", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Nukes (Machine Clears) not related to memory ordering.", + "MetricExpr": "max(tma_machine_clears * (1 - cpu_core@MACHINE_CLEARS.MEMORY_ORDERING@ / cpu_core@MACHINE_CLEARS.COUNT@), 0.0001)", + "MetricGroup": "Machine_Clears;TopdownL3;tma_L3_group;tma_machine_clears_group", + "MetricName": "tma_other_nukes", + "MetricThreshold": "tma_other_nukes > 0.05 & (tma_machine_clears > 0.1 & tma_bad_speculation > 0.15)", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Page Faults", + "MetricExpr": "99 * cpu_core@ASSISTS.PAGE_FAULT@ / tma_info_thread_slots", + "MetricGroup": "TopdownL5;tma_L5_group;tma_assists_group", + "MetricName": "tma_page_faults", + "MetricThreshold": "tma_page_faults > 0.05", + "PublicDescription": "This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Page Faults. A Page Fault may apply on first application access to a memory page. Note operating system handling of page faults accounts for the majority of its cost.", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch)", + "MetricExpr": "cpu_core@UOPS_DISPATCHED.PORT_0@ / tma_info_core_core_clks", + "MetricGroup": "Compute;TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P", + "MetricName": "tma_port_0", + "MetricThreshold": "tma_port_0 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch). Sample with: UOPS_DISPATCHED.PORT_0. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU)", + "MetricExpr": "cpu_core@UOPS_DISPATCHED.PORT_1@ / tma_info_core_core_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P", + "MetricName": "tma_port_1", + "MetricThreshold": "tma_port_1 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU). Sample with: UOPS_DISPATCHED.PORT_1. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_5, tma_port_6, tma_ports_utilized_2", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+] Primary Branch and simple ALU)", + "MetricExpr": "cpu_core@UOPS_DISPATCHED.PORT_6@ / tma_info_core_core_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P", + "MetricName": "tma_port_6", + "MetricThreshold": "tma_port_6 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+] Primary Branch and simple ALU). Sample with: UOPS_DISPATCHED.PORT_6. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_ports_utilized_2", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)", + "MetricExpr": "((tma_ports_utilized_0 * tma_info_thread_clks + (cpu_core@EXE_ACTIVITY.1_PORTS_UTIL@ + tma_retiring * cpu_core@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@)) / tma_info_thread_clks if cpu_core@ARITH.DIV_ACTIVE@ < cpu_core@CYCLE_ACTIVITY.STALLS_TOTAL@ - cpu_core@EXE_ACTIVITY.BOUND_ON_LOADS@ else (cpu_core@EXE_ACTIVITY.1_PORTS_UTIL@ + tma_retiring * cpu_core@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@) / tma_info_thread_clks)", + "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group", + "MetricName": "tma_ports_utilization", + "MetricThreshold": "tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)", + "MetricExpr": "max((cpu_core@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + cpu_core@RS.EMPTY_RESOURCE@) / tma_info_thread_clks, 1) * (cpu_core@CYCLE_ACTIVITY.STALLS_TOTAL@ - cpu_core@EXE_ACTIVITY.BOUND_ON_LOADS@) / tma_info_thread_clks", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_0", + "MetricThreshold": "tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", + "MetricExpr": "cpu_core@EXE_ACTIVITY.1_PORTS_UTIL@ / tma_info_thread_clks", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_issueL1;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_1", + "MetricThreshold": "tma_ports_utilized_1 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful. Sample with: EXE_ACTIVITY.1_PORTS_UTIL. Related metrics: tma_l1_bound", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", + "MetricConstraint": "NO_GROUP_EVENTS_NMI", + "MetricExpr": "cpu_core@EXE_ACTIVITY.2_PORTS_UTIL@ / tma_info_thread_clks", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_issue2P;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_2", + "MetricThreshold": "tma_ports_utilized_2 > 0.15 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop. Sample with: EXE_ACTIVITY.2_PORTS_UTIL. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", + "MetricConstraint": "NO_GROUP_EVENTS_NMI", + "MetricExpr": "cpu_core@UOPS_EXECUTED.CYCLES_GE_3@ / tma_info_thread_clks", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_3m", + "MetricThreshold": "tma_ports_utilized_3m > 0.4 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Sample with: UOPS_EXECUTED.CYCLES_GE_3", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired", + "MetricExpr": "cpu_core@topdown\\-retiring@ / (cpu_core@topdown\\-fe\\-bound@ + cpu_core@topdown\\-bad\\-spec@ + cpu_core@topdown\\-retiring@ + cpu_core@topdown\\-be\\-bound@) + 0 * tma_info_thread_slots", + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_retiring", + "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.1", + "MetricgroupNoGroup": "TopdownL1", + "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.SLOTS", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations", + "MetricExpr": "cpu_core@RESOURCE_STALLS.SCOREBOARD@ / tma_info_thread_clks + tma_c02_wait", + "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group;tma_issueSO", + "MetricName": "tma_serializing_operation", + "MetricThreshold": "tma_serializing_operation > 0.1 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance. Sample with: RESOURCE_STALLS.SCOREBOARD. Related metrics: tma_ms_switches", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring Shuffle operations of 256-bit vector size (FP or Integer)", + "MetricExpr": "tma_light_operations * cpu_core@INT_VEC_RETIRED.SHUFFLES@ / (tma_retiring * tma_info_thread_slots)", + "MetricGroup": "HPC;Pipeline;TopdownL4;tma_L4_group;tma_other_light_ops_group", + "MetricName": "tma_shuffles_256b", + "MetricThreshold": "tma_shuffles_256b > 0.1 & (tma_other_light_ops > 0.3 & tma_light_operations > 0.6)", + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring Shuffle operations of 256-bit vector size (FP or Integer). Shuffles may incur slow cross \"vector lane\" data transfers.", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions", + "MetricConstraint": "NO_GROUP_EVENTS_NMI", + "MetricExpr": "cpu_core@CPU_CLK_UNHALTED.PAUSE@ / tma_info_thread_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_serializing_operation_group", + "MetricName": "tma_slow_pause", + "MetricThreshold": "tma_slow_pause > 0.05 & (tma_serializing_operation > 0.1 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions. Sample with: CPU_CLK_UNHALTED.PAUSE_INST", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary", + "MetricExpr": "MEM_INST_RETIRED.SPLIT_LOADS * min(MEM_INST_RETIRED.SPLIT_LOADS:retire_latency, tma_info_memory_load_miss_real_latency) / tma_info_thread_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_split_loads", + "MetricThreshold": "tma_split_loads > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. Sample with: MEM_INST_RETIRED.SPLIT_LOADS_PS", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric represents rate of split store accesses", + "MetricExpr": "MEM_INST_RETIRED.SPLIT_STORES * min(MEM_INST_RETIRED.SPLIT_STORES:retire_latency, 1) / tma_info_thread_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_issueSpSt;tma_store_bound_group", + "MetricName": "tma_split_stores", + "MetricThreshold": "tma_split_stores > 0.2 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity. Sample with: MEM_INST_RETIRED.SPLIT_STORES_PS. Related metrics: tma_port_4", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)", + "MetricExpr": "(cpu_core@XQ.FULL_CYCLES@ + cpu_core@L1D_PEND_MISS.L2_STALLS@) / tma_info_thread_clks", + "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueBW;tma_l3_bound_group", + "MetricName": "tma_sq_full", + "MetricThreshold": "tma_sq_full > 0.3 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). Related metrics: tma_fb_full, tma_info_bottleneck_cache_memory_bandwidth, tma_mem_bandwidth", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write", + "MetricExpr": "cpu_core@EXE_ACTIVITY.BOUND_ON_STORES@ / tma_info_thread_clks", + "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_store_bound", + "MetricThreshold": "tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck. Sample with: MEM_INST_RETIRED.ALL_STORES_PS", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores", + "MetricExpr": "13 * cpu_core@LD_BLOCKS.STORE_FORWARD@ / tma_info_thread_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_store_fwd_blk", + "MetricThreshold": "tma_store_fwd_blk > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses", + "MetricExpr": "(cpu_core@MEM_STORE_RETIRED.L2_HIT@ * 10 * (1 - cpu_core@MEM_INST_RETIRED.LOCK_LOADS@ / cpu_core@MEM_INST_RETIRED.ALL_STORES@) + (1 - cpu_core@MEM_INST_RETIRED.LOCK_LOADS@ / cpu_core@MEM_INST_RETIRED.ALL_STORES@) * min(cpu_core@CPU_CLK_UNHALTED.THREAD@, cpu_core@OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO@)) / tma_info_thread_clks", + "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_issueSL;tma_store_bound_group", + "MetricName": "tma_store_latency", + "MetricThreshold": "tma_store_latency > 0.1 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full). Related metrics: tma_fb_full, tma_lock_latency", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations", + "MetricExpr": "(cpu_core@UOPS_DISPATCHED.PORT_4_9@ + cpu_core@UOPS_DISPATCHED.PORT_7_8@) / (4 * tma_info_core_core_clks)", + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", + "MetricName": "tma_store_op_utilization", + "MetricThreshold": "tma_store_op_utilization > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations. Sample with: UOPS_DISPATCHED.PORT_7_8", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric roughly estimates the fraction of cycles where the TLB was missed by store accesses, hitting in the second-level TLB (STLB)", + "MetricExpr": "max(0, tma_dtlb_store - tma_store_stlb_miss)", + "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group", + "MetricName": "tma_store_stlb_hit", + "MetricThreshold": "tma_store_stlb_hit > 0.05 & (tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric estimates the fraction of cycles where the STLB was missed by store accesses, performing a hardware page walk", + "MetricExpr": "cpu_core@DTLB_STORE_MISSES.WALK_ACTIVE@ / tma_info_core_core_clks", + "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group", + "MetricName": "tma_store_stlb_miss", + "MetricThreshold": "tma_store_stlb_miss > 0.05 & (tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric estimates how often CPU was stalled due to Streaming store memory accesses; Streaming store optimize out a read request required by RFO stores", + "MetricExpr": "9 * cpu_core@OCR.STREAMING_WR.ANY_RESPONSE@ / tma_info_thread_clks", + "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueSmSt;tma_store_bound_group", + "MetricName": "tma_streaming_stores", + "MetricThreshold": "tma_streaming_stores > 0.2 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates how often CPU was stalled due to Streaming store memory accesses; Streaming store optimize out a read request required by RFO stores. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should Streaming stores be a bottleneck. Sample with: OCR.STREAMING_WR.ANY_RESPONSE. Related metrics: tma_fb_full", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears", + "MetricExpr": "cpu_core@INT_MISC.UNKNOWN_BRANCH_CYCLES@ / tma_info_thread_clks", + "MetricGroup": "BigFootprint;FetchLat;TopdownL4;tma_L4_group;tma_branch_resteers_group", + "MetricName": "tma_unknown_branches", + "MetricThreshold": "tma_unknown_branches > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (e.g. first time the branch is fetched or hitting BTB capacity limit) hence called Unknown Branches. Sample with: FRONTEND_RETIRED.UNKNOWN_BRANCH", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric serves as an approximation of legacy x87 usage", + "MetricExpr": "tma_retiring * cpu_core@UOPS_EXECUTED.X87@ / UOPS_EXECUTED.THREAD", + "MetricGroup": "Compute;TopdownL4;tma_L4_group;tma_fp_arith_group", + "MetricName": "tma_x87_use", + "MetricThreshold": "tma_x87_use > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)", + "PublicDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.", + "ScaleUnit": "100%", + "Unit": "cpu_core" + } +] -- 2.43.0 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [RFC PATCH v2 6/6] perf vendor events intel: Add MTL metric json files 2024-02-28 16:12 ` [RFC PATCH v2 6/6] perf vendor events intel: Add MTL metric json files weilin.wang @ 2024-02-28 16:50 ` Ian Rogers 2024-02-29 1:36 ` Wang, Weilin 0 siblings, 1 reply; 10+ messages in thread From: Ian Rogers @ 2024-02-28 16:50 UTC (permalink / raw) To: weilin.wang Cc: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo, Alexander Shishkin, Jiri Olsa, Namhyung Kim, Adrian Hunter, Kan Liang, linux-perf-users, linux-kernel, Perry Taylor, Samantha Alt, Caleb Biggers On Wed, Feb 28, 2024 at 8:12 AM <weilin.wang@intel.com> wrote: > > From: Weilin Wang <weilin.wang@intel.com> > > Add MTL metric json file at TMA4.7 [1]. Some of the metrics' formulas use TPEBS > retire_latency in MTL. > > [1] https://lore.kernel.org/all/20240214011820.644458-1-irogers@google.com/ > > Signed-off-by: Weilin Wang <weilin.wang@intel.com> > --- > .../arch/x86/meteorlake/metricgroups.json | 127 + > .../arch/x86/meteorlake/mtl-metrics.json | 2531 +++++++++++++++++ > 2 files changed, 2658 insertions(+) > create mode 100644 tools/perf/pmu-events/arch/x86/meteorlake/metricgroups.json > create mode 100644 tools/perf/pmu-events/arch/x86/meteorlake/mtl-metrics.json > > diff --git a/tools/perf/pmu-events/arch/x86/meteorlake/metricgroups.json b/tools/perf/pmu-events/arch/x86/meteorlake/metricgroups.json > new file mode 100644 > index 000000000000..7a03835f262c > --- /dev/null > +++ b/tools/perf/pmu-events/arch/x86/meteorlake/metricgroups.json > @@ -0,0 +1,127 @@ > +{ > + "Backend": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", > + "Bad": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", > + "BadSpec": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", > + "BigFootprint": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", > + "BrMispredicts": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", > + "Branches": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", > + "C0Wait": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", > + "CacheHits": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", > + "CodeGen": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", > + "Compute": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", > + "Cor": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", > + "DSB": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", > + "DSBmiss": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", > + "DataSharing": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", > + "Fed": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", > + "FetchBW": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", > + "FetchLat": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", > + "Flops": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", > + "FpScalar": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", > + "FpVector": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", > + "Frontend": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", > + "HPC": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", > + "IcMiss": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", > + "InsType": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", > + "IntVector": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", > + "L2Evicts": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", > + "LSD": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", > + "MachineClears": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", > + "Machine_Clears": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", > + "Mem": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", > + "MemOffcore": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", > + "MemoryBW": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", > + "MemoryBound": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", > + "MemoryLat": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", > + "MemoryTLB": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", > + "Memory_BW": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", > + "Memory_Lat": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", > + "MicroSeq": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", > + "OS": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", > + "Offcore": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", > + "PGO": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", > + "Pipeline": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", > + "PortsUtil": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", > + "Power": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", > + "Prefetches": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", > + "Ret": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", > + "Retire": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", > + "SMT": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", > + "Server": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", > + "Snoop": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", > + "SoC": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", > + "Summary": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", > + "TmaL1": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", > + "TmaL2": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", > + "TmaL3mem": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", > + "TopdownL1": "Metrics for top-down breakdown at level 1", > + "TopdownL2": "Metrics for top-down breakdown at level 2", > + "TopdownL3": "Metrics for top-down breakdown at level 3", > + "TopdownL4": "Metrics for top-down breakdown at level 4", > + "TopdownL5": "Metrics for top-down breakdown at level 5", > + "TopdownL6": "Metrics for top-down breakdown at level 6", > + "tma_L1_group": "Metrics for top-down breakdown at level 1", > + "tma_L2_group": "Metrics for top-down breakdown at level 2", > + "tma_L3_group": "Metrics for top-down breakdown at level 3", > + "tma_L4_group": "Metrics for top-down breakdown at level 4", > + "tma_L5_group": "Metrics for top-down breakdown at level 5", > + "tma_L6_group": "Metrics for top-down breakdown at level 6", > + "tma_alu_op_utilization_group": "Metrics contributing to tma_alu_op_utilization category", > + "tma_assists_group": "Metrics contributing to tma_assists category", > + "tma_backend_bound_aux_group": "Metrics contributing to tma_backend_bound_aux category", > + "tma_backend_bound_group": "Metrics contributing to tma_backend_bound category", > + "tma_bad_speculation_group": "Metrics contributing to tma_bad_speculation category", > + "tma_base_group": "Metrics contributing to tma_base category", > + "tma_branch_mispredicts_group": "Metrics contributing to tma_branch_mispredicts category", > + "tma_branch_resteers_group": "Metrics contributing to tma_branch_resteers category", > + "tma_core_bound_group": "Metrics contributing to tma_core_bound category", > + "tma_dram_bound_group": "Metrics contributing to tma_dram_bound category", > + "tma_dtlb_load_group": "Metrics contributing to tma_dtlb_load category", > + "tma_dtlb_store_group": "Metrics contributing to tma_dtlb_store category", > + "tma_fetch_bandwidth_group": "Metrics contributing to tma_fetch_bandwidth category", > + "tma_fetch_latency_group": "Metrics contributing to tma_fetch_latency category", > + "tma_fp_arith_group": "Metrics contributing to tma_fp_arith category", > + "tma_fp_vector_group": "Metrics contributing to tma_fp_vector category", > + "tma_frontend_bound_group": "Metrics contributing to tma_frontend_bound category", > + "tma_heavy_operations_group": "Metrics contributing to tma_heavy_operations category", > + "tma_int_operations_group": "Metrics contributing to tma_int_operations category", > + "tma_issue2P": "Metrics related by the issue $issue2P", > + "tma_issueBM": "Metrics related by the issue $issueBM", > + "tma_issueBW": "Metrics related by the issue $issueBW", > + "tma_issueComp": "Metrics related by the issue $issueComp", > + "tma_issueD0": "Metrics related by the issue $issueD0", > + "tma_issueFB": "Metrics related by the issue $issueFB", > + "tma_issueFL": "Metrics related by the issue $issueFL", > + "tma_issueL1": "Metrics related by the issue $issueL1", > + "tma_issueLat": "Metrics related by the issue $issueLat", > + "tma_issueMC": "Metrics related by the issue $issueMC", > + "tma_issueMS": "Metrics related by the issue $issueMS", > + "tma_issueMV": "Metrics related by the issue $issueMV", > + "tma_issueRFO": "Metrics related by the issue $issueRFO", > + "tma_issueSL": "Metrics related by the issue $issueSL", > + "tma_issueSO": "Metrics related by the issue $issueSO", > + "tma_issueSmSt": "Metrics related by the issue $issueSmSt", > + "tma_issueSpSt": "Metrics related by the issue $issueSpSt", > + "tma_issueSyncxn": "Metrics related by the issue $issueSyncxn", > + "tma_issueTLB": "Metrics related by the issue $issueTLB", > + "tma_l1_bound_group": "Metrics contributing to tma_l1_bound category", > + "tma_l3_bound_group": "Metrics contributing to tma_l3_bound category", > + "tma_light_operations_group": "Metrics contributing to tma_light_operations category", > + "tma_load_op_utilization_group": "Metrics contributing to tma_load_op_utilization category", > + "tma_machine_clears_group": "Metrics contributing to tma_machine_clears category", > + "tma_mem_latency_group": "Metrics contributing to tma_mem_latency category", > + "tma_mem_scheduler_group": "Metrics contributing to tma_mem_scheduler category", > + "tma_memory_bound_group": "Metrics contributing to tma_memory_bound category", > + "tma_microcode_sequencer_group": "Metrics contributing to tma_microcode_sequencer category", > + "tma_mite_group": "Metrics contributing to tma_mite category", > + "tma_nuke_group": "Metrics contributing to tma_nuke category", > + "tma_other_light_ops_group": "Metrics contributing to tma_other_light_ops category", > + "tma_ports_utilization_group": "Metrics contributing to tma_ports_utilization category", > + "tma_ports_utilized_0_group": "Metrics contributing to tma_ports_utilized_0 category", > + "tma_ports_utilized_3m_group": "Metrics contributing to tma_ports_utilized_3m category", > + "tma_resource_bound_group": "Metrics contributing to tma_resource_bound category", > + "tma_retiring_group": "Metrics contributing to tma_retiring category", > + "tma_serializing_operation_group": "Metrics contributing to tma_serializing_operation category", > + "tma_store_bound_group": "Metrics contributing to tma_store_bound category", > + "tma_store_op_utilization_group": "Metrics contributing to tma_store_op_utilization category" > +} > diff --git a/tools/perf/pmu-events/arch/x86/meteorlake/mtl-metrics.json b/tools/perf/pmu-events/arch/x86/meteorlake/mtl-metrics.json > new file mode 100644 > index 000000000000..12df19538fd6 > --- /dev/null > +++ b/tools/perf/pmu-events/arch/x86/meteorlake/mtl-metrics.json > @@ -0,0 +1,2531 @@ > +[ > + { > + "BriefDescription": "C10 residency percent per package", > + "MetricExpr": "cstate_pkg@c10\\-residency@ / TSC", > + "MetricGroup": "Power", > + "MetricName": "C10_Pkg_Residency", > + "ScaleUnit": "100%" > + }, > + { > + "BriefDescription": "C1 residency percent per core", > + "MetricExpr": "cstate_core@c1\\-residency@ / TSC", > + "MetricGroup": "Power", > + "MetricName": "C1_Core_Residency", > + "ScaleUnit": "100%" > + }, > + { > + "BriefDescription": "C2 residency percent per package", > + "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC", > + "MetricGroup": "Power", > + "MetricName": "C2_Pkg_Residency", > + "ScaleUnit": "100%" > + }, > + { > + "BriefDescription": "C3 residency percent per package", > + "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC", > + "MetricGroup": "Power", > + "MetricName": "C3_Pkg_Residency", > + "ScaleUnit": "100%" > + }, > + { > + "BriefDescription": "C6 residency percent per core", > + "MetricExpr": "cstate_core@c6\\-residency@ / TSC", > + "MetricGroup": "Power", > + "MetricName": "C6_Core_Residency", > + "ScaleUnit": "100%" > + }, > + { > + "BriefDescription": "C6 residency percent per package", > + "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC", > + "MetricGroup": "Power", > + "MetricName": "C6_Pkg_Residency", > + "ScaleUnit": "100%" > + }, > + { > + "BriefDescription": "C7 residency percent per core", > + "MetricExpr": "cstate_core@c7\\-residency@ / TSC", > + "MetricGroup": "Power", > + "MetricName": "C7_Core_Residency", > + "ScaleUnit": "100%" > + }, > + { > + "BriefDescription": "C7 residency percent per package", > + "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC", > + "MetricGroup": "Power", > + "MetricName": "C7_Pkg_Residency", > + "ScaleUnit": "100%" > + }, > + { > + "BriefDescription": "C8 residency percent per package", > + "MetricExpr": "cstate_pkg@c8\\-residency@ / TSC", > + "MetricGroup": "Power", > + "MetricName": "C8_Pkg_Residency", > + "ScaleUnit": "100%" > + }, > + { > + "BriefDescription": "C9 residency percent per package", > + "MetricExpr": "cstate_pkg@c9\\-residency@ / TSC", > + "MetricGroup": "Power", > + "MetricName": "C9_Pkg_Residency", > + "ScaleUnit": "100%" > + }, > + { > + "BriefDescription": "Percentage of cycles spent in System Management Interrupts.", > + "MetricExpr": "((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0 else 0)", > + "MetricGroup": "smi", > + "MetricName": "smi_cycles", > + "MetricThreshold": "smi_cycles > 0.1", > + "ScaleUnit": "100%" > + }, > + { > + "BriefDescription": "Number of SMI interrupts.", > + "MetricExpr": "msr@smi@", > + "MetricGroup": "smi", > + "MetricName": "smi_num", > + "ScaleUnit": "1SMI#" > + }, > + { > + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to certain allocation restrictions.", > + "MetricExpr": "cpu_atom@TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS@ / tma_info_core_slots", > + "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group", > + "MetricName": "tma_alloc_restriction", > + "MetricThreshold": "tma_alloc_restriction > 0.1", > + "ScaleUnit": "100%", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls", > + "MetricExpr": "cpu_atom@TOPDOWN_BE_BOUND.ALL@ / tma_info_core_slots", > + "MetricGroup": "TopdownL1;tma_L1_group", > + "MetricName": "tma_backend_bound", > + "MetricThreshold": "tma_backend_bound > 0.1", > + "MetricgroupNoGroup": "TopdownL1", > + "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls. Note that uops must be available for consumption in order for this event to count. If a uop is not available (IQ is empty), this event will not count. The rest of these subevents count backend stalls, in cycles, due to an outstanding request which is memory bound vs core bound. The subevents are not slot based events and therefore can not be precisely added or subtracted from the Backend_Bound_Aux subevents which are slot based.", > + "ScaleUnit": "100%", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls", > + "MetricExpr": "tma_backend_bound", > + "MetricGroup": "TopdownL1;tma_L1_group", > + "MetricName": "tma_backend_bound_aux", > + "MetricThreshold": "tma_backend_bound_aux > 0.2", > + "MetricgroupNoGroup": "TopdownL1", > + "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls. Note that UOPS must be available for consumption in order for this event to count. If a uop is not available (IQ is empty), this event will not count. All of these subevents count backend stalls, in slots, due to a resource limitation. These are not cycle based events and therefore can not be precisely added or subtracted from the Backend_Bound subevents which are cycle based. These subevents are supplementary to Backend_Bound and can be used to analyze results from a resource perspective at allocation.", > + "ScaleUnit": "100%", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear", > + "MetricExpr": "cpu_atom@TOPDOWN_BAD_SPECULATION.ALL@ / tma_info_core_slots", > + "MetricGroup": "TopdownL1;tma_L1_group", > + "MetricName": "tma_bad_speculation", > + "MetricThreshold": "tma_bad_speculation > 0.15", > + "MetricgroupNoGroup": "TopdownL1", > + "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ). Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear.", > + "ScaleUnit": "100%", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Counts the number of uops that are not from the microsequencer.", > + "MetricExpr": "(cpu_atom@TOPDOWN_RETIRING.ALL@ - cpu_atom@UOPS_RETIRED.MS@) / tma_info_core_slots", > + "MetricGroup": "TopdownL2;tma_L2_group;tma_retiring_group", > + "MetricName": "tma_base", > + "MetricThreshold": "tma_base > 0.6", > + "MetricgroupNoGroup": "TopdownL2", > + "ScaleUnit": "100%", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend", > + "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.BRANCH_DETECT@ / tma_info_core_slots", > + "MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_latency_group", > + "MetricName": "tma_branch_detect", > + "MetricThreshold": "tma_branch_detect > 0.05", > + "PublicDescription": "Counts the number of issue slots that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.", > + "ScaleUnit": "100%", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to branch mispredicts.", > + "MetricExpr": "cpu_atom@TOPDOWN_BAD_SPECULATION.MISPREDICT@ / tma_info_core_slots", > + "MetricGroup": "TopdownL2;tma_L2_group;tma_bad_speculation_group", > + "MetricName": "tma_branch_mispredicts", > + "MetricThreshold": "tma_branch_mispredicts > 0.05", > + "MetricgroupNoGroup": "TopdownL2", > + "ScaleUnit": "100%", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch.", > + "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.BRANCH_RESTEER@ / tma_info_core_slots", > + "MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_latency_group", > + "MetricName": "tma_branch_resteer", > + "MetricThreshold": "tma_branch_resteer > 0.05", > + "ScaleUnit": "100%", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to the microcode sequencer (MS).", > + "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.CISC@ / tma_info_core_slots", > + "MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", > + "MetricName": "tma_cisc", > + "MetricThreshold": "tma_cisc > 0.05", > + "ScaleUnit": "100%", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Counts the number of cycles due to backend bound stalls that are core execution bound and not attributed to outstanding demand load or store stalls.", > + "MetricExpr": "max(0, tma_backend_bound - tma_memory_bound)", > + "MetricGroup": "TopdownL2;tma_L2_group;tma_backend_bound_group", > + "MetricName": "tma_core_bound", > + "MetricThreshold": "tma_core_bound > 0.1", > + "MetricgroupNoGroup": "TopdownL2", > + "ScaleUnit": "100%", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to decode stalls.", > + "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.DECODE@ / tma_info_core_slots", > + "MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", > + "MetricName": "tma_decode", > + "MetricThreshold": "tma_decode > 0.05", > + "ScaleUnit": "100%", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Counts the number of machine clears relative to the number of nuke slots due to memory disambiguation.", > + "MetricExpr": "tma_nuke * (cpu_atom@MACHINE_CLEARS.DISAMBIGUATION@ / cpu_atom@MACHINE_CLEARS.SLOW@)", > + "MetricGroup": "TopdownL4;tma_L4_group;tma_nuke_group", > + "MetricName": "tma_disambiguation", > + "MetricThreshold": "tma_disambiguation > 0.02", > + "ScaleUnit": "100%", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (Non-DRAM).", > + "MetricExpr": "cpu_atom@MEM_BOUND_STALLS_LOAD.LLC_MISS@ / tma_info_core_clks - max((cpu_atom@MEM_BOUND_STALLS_LOAD.ALL@ - cpu_atom@LD_HEAD.L1_MISS_AT_RET@) / tma_info_core_clks, 0) * cpu_atom@MEM_BOUND_STALLS_LOAD.LLC_MISS@ / cpu_atom@MEM_BOUND_STALLS_LOAD.ALL@", > + "MetricGroup": "TopdownL3;tma_L3_group;tma_memory_bound_group", > + "MetricName": "tma_dram_bound", > + "MetricThreshold": "tma_dram_bound > 0.1", > + "ScaleUnit": "100%", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to a machine clear classified as a fast nuke due to memory ordering, memory disambiguation and memory renaming.", > + "MetricExpr": "cpu_atom@TOPDOWN_BAD_SPECULATION.FASTNUKE@ / tma_info_core_slots", > + "MetricGroup": "TopdownL3;tma_L3_group;tma_machine_clears_group", > + "MetricName": "tma_fast_nuke", > + "MetricThreshold": "tma_fast_nuke > 0.05", > + "ScaleUnit": "100%", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations.", > + "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH@ / tma_info_core_slots", > + "MetricGroup": "TopdownL2;tma_L2_group;tma_frontend_bound_group", > + "MetricName": "tma_fetch_bandwidth", > + "MetricThreshold": "tma_fetch_bandwidth > 0.1", > + "MetricgroupNoGroup": "TopdownL2", > + "ScaleUnit": "100%", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations.", > + "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.FRONTEND_LATENCY@ / tma_info_core_slots", > + "MetricGroup": "TopdownL2;tma_L2_group;tma_frontend_bound_group", > + "MetricName": "tma_fetch_latency", > + "MetricThreshold": "tma_fetch_latency > 0.15", > + "MetricgroupNoGroup": "TopdownL2", > + "ScaleUnit": "100%", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Counts the number of machine clears relative to the number of nuke slots due to FP assists.", > + "MetricExpr": "tma_nuke * (cpu_atom@MACHINE_CLEARS.FP_ASSIST@ / cpu_atom@MACHINE_CLEARS.SLOW@)", > + "MetricGroup": "TopdownL4;tma_L4_group;tma_nuke_group", > + "MetricName": "tma_fp_assist", > + "MetricThreshold": "tma_fp_assist > 0.02", > + "ScaleUnit": "100%", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Counts the number of floating point divide operations per uop.", > + "MetricExpr": "cpu_atom@UOPS_RETIRED.FPDIV@ / tma_info_core_slots", > + "MetricGroup": "TopdownL3;tma_L3_group;tma_base_group", > + "MetricName": "tma_fpdiv_uops", > + "MetricThreshold": "tma_fpdiv_uops > 0.2", > + "ScaleUnit": "100%", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to frontend stalls.", > + "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.ALL@ / tma_info_core_slots", > + "MetricGroup": "TopdownL1;tma_L1_group", > + "MetricName": "tma_frontend_bound", > + "MetricThreshold": "tma_frontend_bound > 0.2", > + "MetricgroupNoGroup": "TopdownL1", > + "ScaleUnit": "100%", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to instruction cache misses.", > + "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.ICACHE@ / tma_info_core_slots", > + "MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_latency_group", > + "MetricName": "tma_icache_misses", > + "MetricThreshold": "tma_icache_misses > 0.05", > + "ScaleUnit": "100%", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "", > + "MetricExpr": "cpu_atom@CPU_CLK_UNHALTED.CORE@", > + "MetricName": "tma_info_core_clks", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "", > + "MetricExpr": "cpu_atom@CPU_CLK_UNHALTED.CORE_P@", > + "MetricName": "tma_info_core_clks_p", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Cycles Per Instruction", > + "MetricExpr": "tma_info_core_clks / INST_RETIRED.ANY", > + "MetricName": "tma_info_core_cpi", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Instructions Per Cycle", > + "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / tma_info_core_clks", > + "MetricName": "tma_info_core_ipc", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "", > + "MetricExpr": "6 * tma_info_core_clks", > + "MetricName": "tma_info_core_slots", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Uops Per Instruction", > + "MetricExpr": "cpu_atom@UOPS_RETIRED.ALL@ / INST_RETIRED.ANY", > + "MetricName": "tma_info_core_upi", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Percent of instruction miss cost that hit in DRAM", > + "MetricExpr": "100 * cpu_atom@MEM_BOUND_STALLS_IFETCH.LLC_MISS@ / cpu_atom@MEM_BOUND_STALLS_IFETCH.ALL@", > + "MetricName": "tma_info_frontend_inst_miss_cost_dramhit_percent", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Percent of instruction miss cost that hit in the L2", > + "MetricExpr": "100 * cpu_atom@MEM_BOUND_STALLS_IFETCH.L2_HIT@ / cpu_atom@MEM_BOUND_STALLS_IFETCH.ALL@", > + "MetricName": "tma_info_frontend_inst_miss_cost_l2hit_percent", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Percent of instruction miss cost that hit in the L3", > + "MetricExpr": "100 * cpu_atom@MEM_BOUND_STALLS_IFETCH.LLC_HIT@ / cpu_atom@MEM_BOUND_STALLS_IFETCH.ALL@", > + "MetricName": "tma_info_frontend_inst_miss_cost_l3hit_percent", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Ratio of all branches which mispredict", > + "MetricExpr": "cpu_atom@BR_MISP_RETIRED.ALL_BRANCHES@ / BR_INST_RETIRED.ALL_BRANCHES", > + "MetricName": "tma_info_inst_mix_branch_mispredict_ratio", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Ratio between Mispredicted branches and unknown branches", > + "MetricExpr": "cpu_atom@BR_MISP_RETIRED.ALL_BRANCHES@ / BACLEARS.ANY", > + "MetricName": "tma_info_inst_mix_branch_mispredict_to_unknown_branch_ratio", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Percentage of all uops which are FPDiv uops", > + "MetricExpr": "100 * cpu_atom@UOPS_RETIRED.FPDIV@ / UOPS_RETIRED.ALL", > + "MetricName": "tma_info_inst_mix_fpdiv_uop_ratio", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Percentage of all uops which are IDiv uops", > + "MetricExpr": "100 * cpu_atom@UOPS_RETIRED.IDIV@ / UOPS_RETIRED.ALL", > + "MetricName": "tma_info_inst_mix_idiv_uop_ratio", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", > + "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / BR_INST_RETIRED.ALL_BRANCHES", > + "MetricName": "tma_info_inst_mix_ipbranch", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Instruction per (near) call (lower number means higher occurrence rate)", > + "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / BR_INST_RETIRED.NEAR_CALL", > + "MetricName": "tma_info_inst_mix_ipcall", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Instructions per Far Branch", > + "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / (cpu_atom@BR_INST_RETIRED.FAR_BRANCH@ / 2)", > + "MetricName": "tma_info_inst_mix_ipfarbranch", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Instructions per Load", > + "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / MEM_UOPS_RETIRED.ALL_LOADS", > + "MetricName": "tma_info_inst_mix_ipload", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Instructions per retired conditional Branch Misprediction where the branch was not taken", > + "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / (cpu_atom@BR_MISP_RETIRED.COND@ - cpu_atom@BR_MISP_RETIRED.COND_TAKEN@)", > + "MetricName": "tma_info_inst_mix_ipmisp_cond_ntaken", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Instructions per retired conditional Branch Misprediction where the branch was taken", > + "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / BR_MISP_RETIRED.COND_TAKEN", > + "MetricName": "tma_info_inst_mix_ipmisp_cond_taken", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Instructions per retired indirect call or jump Branch Misprediction", > + "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / BR_MISP_RETIRED.INDIRECT", > + "MetricName": "tma_info_inst_mix_ipmisp_indirect", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Instructions per retired return Branch Misprediction", > + "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / BR_MISP_RETIRED.RETURN", > + "MetricName": "tma_info_inst_mix_ipmisp_ret", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Instructions per retired Branch Misprediction", > + "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / BR_MISP_RETIRED.ALL_BRANCHES", > + "MetricName": "tma_info_inst_mix_ipmispredict", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Instructions per Store", > + "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / MEM_UOPS_RETIRED.ALL_STORES", > + "MetricName": "tma_info_inst_mix_ipstore", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Percentage of all uops which are ucode ops", > + "MetricExpr": "100 * cpu_atom@UOPS_RETIRED.MS@ / UOPS_RETIRED.ALL", > + "MetricName": "tma_info_inst_mix_microcode_uop_ratio", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Percentage of all uops which are x87 uops", > + "MetricExpr": "100 * cpu_atom@UOPS_RETIRED.X87@ / UOPS_RETIRED.ALL", > + "MetricName": "tma_info_inst_mix_x87_uop_ratio", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Percentage of total non-speculative loads with a address aliasing block", > + "MetricExpr": "100 * cpu_atom@LD_BLOCKS.ADDRESS_ALIAS@ / MEM_UOPS_RETIRED.ALL_LOADS", > + "MetricName": "tma_info_l1_bound_address_alias_blocks", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Percentage of total non-speculative loads that are splits", > + "MetricExpr": "100 * cpu_atom@MEM_UOPS_RETIRED.SPLIT_LOADS@ / MEM_UOPS_RETIRED.ALL_LOADS", > + "MetricName": "tma_info_l1_bound_load_splits", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Percentage of total non-speculative loads with a store forward or unknown store address block", > + "MetricExpr": "100 * cpu_atom@LD_BLOCKS.DATA_UNKNOWN@ / MEM_UOPS_RETIRED.ALL_LOADS", > + "MetricName": "tma_info_l1_bound_store_fwd_blocks", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Cycle cost per L2 hit", > + "MetricExpr": "cpu_atom@MEM_BOUND_STALLS_LOAD.L2_HIT@ / MEM_LOAD_UOPS_RETIRED.L2_HIT", > + "MetricName": "tma_info_memory_cycles_per_demand_load_l2_hit", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Cycle cost per LLC hit", > + "MetricExpr": "cpu_atom@MEM_BOUND_STALLS_LOAD.LLC_HIT@ / MEM_LOAD_UOPS_RETIRED.L3_HIT", > + "MetricName": "tma_info_memory_cycles_per_demand_load_l3_hit", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "load ops retired per 1000 instruction", > + "MetricExpr": "1e3 * cpu_atom@MEM_UOPS_RETIRED.ALL_LOADS@ / INST_RETIRED.ANY", > + "MetricName": "tma_info_memory_memloadpki", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Average CPU Utilization", > + "MetricExpr": "cpu_atom@CPU_CLK_UNHALTED.REF_TSC@ / TSC", > + "MetricName": "tma_info_system_cpu_utilization", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Fraction of cycles spent in Kernel mode", > + "MetricExpr": "cpu_atom@CPU_CLK_UNHALTED.CORE@k / CPU_CLK_UNHALTED.CORE", > + "MetricGroup": "Summary", > + "MetricName": "tma_info_system_kernel_utilization", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Average Frequency Utilization relative nominal frequency", > + "MetricExpr": "tma_info_core_clks / CPU_CLK_UNHALTED.REF_TSC", > + "MetricGroup": "Power", > + "MetricName": "tma_info_system_turbo_utilization", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) misses.", > + "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.ITLB_MISS@ / tma_info_core_slots", > + "MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_latency_group", > + "MetricName": "tma_itlb_misses", > + "MetricThreshold": "tma_itlb_misses > 0.05", > + "ScaleUnit": "100%", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a load block.", > + "MetricExpr": "cpu_atom@LD_HEAD.L1_BOUND_AT_RET@ / tma_info_core_clks", > + "MetricGroup": "TopdownL3;tma_L3_group;tma_memory_bound_group", > + "MetricName": "tma_l1_bound", > + "MetricThreshold": "tma_l1_bound > 0.1", > + "ScaleUnit": "100%", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Counts the number of cycles a core is stalled due to a demand load which hit in the L2 Cache.", > + "MetricExpr": "cpu_atom@MEM_BOUND_STALLS_LOAD.L2_HIT@ / tma_info_core_clks - max((cpu_atom@MEM_BOUND_STALLS_LOAD.ALL@ - cpu_atom@LD_HEAD.L1_MISS_AT_RET@) / tma_info_core_clks, 0) * cpu_atom@MEM_BOUND_STALLS_LOAD.L2_HIT@ / cpu_atom@MEM_BOUND_STALLS_LOAD.ALL@", > + "MetricGroup": "TopdownL3;tma_L3_group;tma_memory_bound_group", > + "MetricName": "tma_l2_bound", > + "MetricThreshold": "tma_l2_bound > 0.1", > + "ScaleUnit": "100%", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Counts the number of cycles a core is stalled due to a demand load which hit in the Last Level Cache (LLC) or other core with HITE/F/M.", > + "MetricExpr": "cpu_atom@MEM_BOUND_STALLS_LOAD.LLC_HIT@ / tma_info_core_clks - max((cpu_atom@MEM_BOUND_STALLS_LOAD.ALL@ - cpu_atom@LD_HEAD.L1_MISS_AT_RET@) / tma_info_core_clks, 0) * cpu_atom@MEM_BOUND_STALLS_LOAD.LLC_HIT@ / cpu_atom@MEM_BOUND_STALLS_LOAD.ALL@", > + "MetricGroup": "TopdownL3;tma_L3_group;tma_memory_bound_group", > + "MetricName": "tma_l3_bound", > + "MetricThreshold": "tma_l3_bound > 0.1", > + "ScaleUnit": "100%", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Counts the number of cycles, relative to the number of mem_scheduler slots, in which uops are blocked due to load buffer full", > + "MetricExpr": "tma_mem_scheduler * cpu_atom@MEM_SCHEDULER_BLOCK.LD_BUF@ / MEM_SCHEDULER_BLOCK.ALL", > + "MetricGroup": "TopdownL4;tma_L4_group;tma_mem_scheduler_group", > + "MetricName": "tma_ld_buffer", > + "MetricThreshold": "tma_ld_buffer > 0.05", > + "ScaleUnit": "100%", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation.", > + "MetricExpr": "cpu_atom@TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS@ / tma_info_core_slots", > + "MetricGroup": "TopdownL2;tma_L2_group;tma_bad_speculation_group", > + "MetricName": "tma_machine_clears", > + "MetricThreshold": "tma_machine_clears > 0.05", > + "MetricgroupNoGroup": "TopdownL2", > + "ScaleUnit": "100%", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops.", > + "MetricExpr": "cpu_atom@TOPDOWN_BE_BOUND.MEM_SCHEDULER@ / tma_info_core_slots", > + "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group", > + "MetricName": "tma_mem_scheduler", > + "MetricThreshold": "tma_mem_scheduler > 0.1", > + "ScaleUnit": "100%", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Counts the number of cycles the core is stalled due to stores or loads.", > + "MetricExpr": "min(tma_backend_bound, cpu_atom@LD_HEAD.ANY_AT_RET@ / tma_info_core_clks + tma_store_bound)", > + "MetricGroup": "TopdownL2;tma_L2_group;tma_backend_bound_group", > + "MetricName": "tma_memory_bound", > + "MetricThreshold": "tma_memory_bound > 0.2", > + "MetricgroupNoGroup": "TopdownL2", > + "ScaleUnit": "100%", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Counts the number of machine clears relative to the number of nuke slots due to memory ordering.", > + "MetricExpr": "tma_nuke * (cpu_atom@MACHINE_CLEARS.MEMORY_ORDERING@ / cpu_atom@MACHINE_CLEARS.SLOW@)", > + "MetricGroup": "TopdownL4;tma_L4_group;tma_nuke_group", > + "MetricName": "tma_memory_ordering", > + "MetricThreshold": "tma_memory_ordering > 0.02", > + "ScaleUnit": "100%", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Counts the number of uops that are from the complex flows issued by the micro-sequencer (MS)", > + "MetricExpr": "cpu_atom@UOPS_RETIRED.MS@ / tma_info_core_slots", > + "MetricGroup": "TopdownL2;tma_L2_group;tma_retiring_group", > + "MetricName": "tma_ms_uops", > + "MetricThreshold": "tma_ms_uops > 0.05", > + "MetricgroupNoGroup": "TopdownL2", > + "PublicDescription": "Counts the number of uops that are from the complex flows issued by the micro-sequencer (MS). This includes uops from flows due to complex instructions, faults, assists, and inserted flows.", > + "ScaleUnit": "100%", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops.", > + "MetricExpr": "cpu_atom@TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER@ / tma_info_core_slots", > + "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group", > + "MetricName": "tma_non_mem_scheduler", > + "MetricThreshold": "tma_non_mem_scheduler > 0.1", > + "ScaleUnit": "100%", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to a machine clear (slow nuke).", > + "MetricExpr": "cpu_atom@TOPDOWN_BAD_SPECULATION.NUKE@ / tma_info_core_slots", > + "MetricGroup": "TopdownL3;tma_L3_group;tma_machine_clears_group", > + "MetricName": "tma_nuke", > + "MetricThreshold": "tma_nuke > 0.05", > + "ScaleUnit": "100%", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to other common frontend stalls not categorized.", > + "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.OTHER@ / tma_info_core_slots", > + "MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", > + "MetricName": "tma_other_fb", > + "MetricThreshold": "tma_other_fb > 0.05", > + "ScaleUnit": "100%", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a number of other load blocks.", > + "MetricExpr": "cpu_atom@LD_HEAD.OTHER_AT_RET@ / tma_info_core_clks", > + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", > + "MetricName": "tma_other_l1", > + "MetricThreshold": "tma_other_l1 > 0.05", > + "ScaleUnit": "100%", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hits in the L2, LLC, DRAM or MMIO (Non-DRAM) but could not be correctly attributed or cycles in which the load miss is waiting on a request buffer.", > + "MetricExpr": "max(0, tma_memory_bound - (tma_store_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound))", > + "MetricGroup": "TopdownL3;tma_L3_group;tma_memory_bound_group", > + "MetricName": "tma_other_load_store", > + "MetricThreshold": "tma_other_load_store > 0.1", > + "ScaleUnit": "100%", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Counts the number of uops retired excluding ms and fp div uops.", > + "MetricExpr": "(cpu_atom@TOPDOWN_RETIRING.ALL@ - cpu_atom@UOPS_RETIRED.MS@ - cpu_atom@UOPS_RETIRED.FPDIV@) / tma_info_core_slots", > + "MetricGroup": "TopdownL3;tma_L3_group;tma_base_group", > + "MetricName": "tma_other_ret", > + "MetricThreshold": "tma_other_ret > 0.3", > + "ScaleUnit": "100%", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Counts the number of machine clears relative to the number of nuke slots due to page faults.", > + "MetricExpr": "tma_nuke * (cpu_atom@MACHINE_CLEARS.PAGE_FAULT@ / cpu_atom@MACHINE_CLEARS.SLOW@)", > + "MetricGroup": "TopdownL4;tma_L4_group;tma_nuke_group", > + "MetricName": "tma_page_fault", > + "MetricThreshold": "tma_page_fault > 0.02", > + "ScaleUnit": "100%", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to wrong predecodes.", > + "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.PREDECODE@ / tma_info_core_slots", > + "MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", > + "MetricName": "tma_predecode", > + "MetricThreshold": "tma_predecode > 0.05", > + "ScaleUnit": "100%", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls).", > + "MetricExpr": "cpu_atom@TOPDOWN_BE_BOUND.REGISTER@ / tma_info_core_slots", > + "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group", > + "MetricName": "tma_register", > + "MetricThreshold": "tma_register > 0.1", > + "ScaleUnit": "100%", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to the reorder buffer being full (ROB stalls).", > + "MetricExpr": "cpu_atom@TOPDOWN_BE_BOUND.REORDER_BUFFER@ / tma_info_core_slots", > + "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group", > + "MetricName": "tma_reorder_buffer", > + "MetricThreshold": "tma_reorder_buffer > 0.1", > + "ScaleUnit": "100%", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls", > + "MetricExpr": "tma_backend_bound", > + "MetricGroup": "TopdownL2;tma_L2_group;tma_backend_bound_aux_group", > + "MetricName": "tma_resource_bound", > + "MetricThreshold": "tma_resource_bound > 0.2", > + "MetricgroupNoGroup": "TopdownL2", > + "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls. Note that uops must be available for consumption in order for this event to count. If a uop is not available (IQ is empty), this event will not count.", > + "ScaleUnit": "100%", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Counts the number of issue slots that result in retirement slots.", > + "MetricExpr": "cpu_atom@TOPDOWN_RETIRING.ALL@ / tma_info_core_slots", > + "MetricGroup": "TopdownL1;tma_L1_group", > + "MetricName": "tma_retiring", > + "MetricThreshold": "tma_retiring > 0.75", > + "MetricgroupNoGroup": "TopdownL1", > + "ScaleUnit": "100%", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Counts the number of cycles, relative to the number of mem_scheduler slots, in which uops are blocked due to RSV full relative", > + "MetricExpr": "tma_mem_scheduler * cpu_atom@MEM_SCHEDULER_BLOCK.RSV@ / MEM_SCHEDULER_BLOCK.ALL", > + "MetricGroup": "TopdownL4;tma_L4_group;tma_mem_scheduler_group", > + "MetricName": "tma_rsv", > + "MetricThreshold": "tma_rsv > 0.05", > + "ScaleUnit": "100%", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS).", > + "MetricExpr": "cpu_atom@TOPDOWN_BE_BOUND.SERIALIZATION@ / tma_info_core_slots", > + "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group", > + "MetricName": "tma_serialization", > + "MetricThreshold": "tma_serialization > 0.1", > + "ScaleUnit": "100%", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Counts the number of machine clears relative to the number of nuke slots due to SMC.", > + "MetricExpr": "tma_nuke * (cpu_atom@MACHINE_CLEARS.SMC@ / cpu_atom@MACHINE_CLEARS.SLOW@)", > + "MetricGroup": "TopdownL4;tma_L4_group;tma_nuke_group", > + "MetricName": "tma_smc", > + "MetricThreshold": "tma_smc > 0.02", > + "ScaleUnit": "100%", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Counts the number of cycles, relative to the number of mem_scheduler slots, in which uops are blocked due to store buffer full", > + "MetricExpr": "tma_store_bound", > + "MetricGroup": "TopdownL4;tma_L4_group;tma_mem_scheduler_group", > + "MetricName": "tma_st_buffer", > + "MetricThreshold": "tma_st_buffer > 0.05", > + "ScaleUnit": "100%", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a first level TLB miss.", > + "MetricExpr": "cpu_atom@LD_HEAD.DTLB_MISS_AT_RET@ / tma_info_core_clks", > + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", > + "MetricName": "tma_stlb_hit", > + "MetricThreshold": "tma_stlb_hit > 0.05", > + "ScaleUnit": "100%", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a second level TLB miss requiring a page walk.", > + "MetricExpr": "cpu_atom@LD_HEAD.PGWALK_AT_RET@ / tma_info_core_clks", > + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", > + "MetricName": "tma_stlb_miss", > + "MetricThreshold": "tma_stlb_miss > 0.05", > + "ScaleUnit": "100%", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Counts the number of cycles the core is stalled due to store buffer full.", > + "MetricExpr": "tma_mem_scheduler * (cpu_atom@MEM_SCHEDULER_BLOCK.ST_BUF@ / cpu_atom@MEM_SCHEDULER_BLOCK.ALL@)", > + "MetricGroup": "TopdownL3;tma_L3_group;tma_memory_bound_group", > + "MetricName": "tma_store_bound", > + "MetricThreshold": "tma_store_bound > 0.1", > + "ScaleUnit": "100%", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a store forward block.", > + "MetricExpr": "cpu_atom@LD_HEAD.ST_ADDR_AT_RET@ / tma_info_core_clks", > + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", > + "MetricName": "tma_store_fwd_blk", > + "MetricThreshold": "tma_store_fwd_blk > 0.05", > + "ScaleUnit": "100%", > + "Unit": "cpu_atom" > + }, > + { > + "BriefDescription": "Uncore frequency per die [GHZ]", > + "MetricExpr": "tma_info_system_socket_clks / #num_dies / duration_time / 1e9", > + "MetricGroup": "SoC", > + "MetricName": "UNCORE_FREQ", > + "Unit": "cpu_core" > + }, > + { > + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.", > + "MetricExpr": "(cpu_core@UOPS_DISPATCHED.PORT_0@ + cpu_core@UOPS_DISPATCHED.PORT_1@ + cpu_core@UOPS_DISPATCHED.PORT_5_11@ + cpu_core@UOPS_DISPATCHED.PORT_6@) / (5 * tma_info_core_core_clks)", > + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", > + "MetricName": "tma_alu_op_utilization", > + "MetricThreshold": "tma_alu_op_utilization > 0.4", > + "ScaleUnit": "100%", > + "Unit": "cpu_core" > + }, > + { > + "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists", > + "MetricExpr": "78 * cpu_core@ASSISTS.ANY@ / tma_info_thread_slots", > + "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group", > + "MetricName": "tma_assists", > + "MetricThreshold": "tma_assists > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1)", > + "PublicDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases. Sample with: ASSISTS.ANY", > + "ScaleUnit": "100%", > + "Unit": "cpu_core" > + }, > + { > + "BriefDescription": "This metric estimates fraction of slots the CPU retired uops as a result of handing SSE to AVX* or AVX* to SSE transition Assists.", > + "MetricExpr": "63 * cpu_core@ASSISTS.SSE_AVX_MIX@ / tma_info_thread_slots", > + "MetricGroup": "HPC;TopdownL5;tma_L5_group;tma_assists_group", > + "MetricName": "tma_avx_assists", > + "MetricThreshold": "tma_avx_assists > 0.1", > + "ScaleUnit": "100%", > + "Unit": "cpu_core" > + }, > + { > + "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend", > + "MetricExpr": "cpu_core@topdown\\-be\\-bound@ / (cpu_core@topdown\\-fe\\-bound@ + cpu_core@topdown\\-bad\\-spec@ + cpu_core@topdown\\-retiring@ + cpu_core@topdown\\-be\\-bound@) + 0 * tma_info_thread_slots", > + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", > + "MetricName": "tma_backend_bound", > + "MetricThreshold": "tma_backend_bound > 0.2", > + "MetricgroupNoGroup": "TopdownL1", > + "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. Sample with: TOPDOWN.BACKEND_BOUND_SLOTS", > + "ScaleUnit": "100%", > + "Unit": "cpu_core" > + }, > + { > + "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations", > + "MetricExpr": "max(1 - (tma_frontend_bound + tma_backend_bound + tma_retiring), 0)", > + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", > + "MetricName": "tma_bad_speculation", > + "MetricThreshold": "tma_bad_speculation > 0.15", > + "MetricgroupNoGroup": "TopdownL1", > + "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", > + "ScaleUnit": "100%", > + "Unit": "cpu_core" > + }, > + { > + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction", > + "MetricExpr": "cpu_core@topdown\\-br\\-mispredict@ / (cpu_core@topdown\\-fe\\-bound@ + cpu_core@topdown\\-bad\\-spec@ + cpu_core@topdown\\-retiring@ + cpu_core@topdown\\-be\\-bound@) + 0 * tma_info_thread_slots", > + "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueBM", > + "MetricName": "tma_branch_mispredicts", > + "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15", > + "MetricgroupNoGroup": "TopdownL2", > + "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: TOPDOWN.BR_MISPREDICT_SLOTS. Related metrics: tma_info_bad_spec_branch_misprediction_cost, tma_info_bottleneck_mispredictions, tma_mispredicts_resteers", > + "ScaleUnit": "100%", > + "Unit": "cpu_core" > + }, > + { > + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers", > + "MetricExpr": "cpu_core@INT_MISC.CLEAR_RESTEER_CYCLES@ / tma_info_thread_clks + tma_unknown_branches", > + "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group", > + "MetricName": "tma_branch_resteers", > + "MetricThreshold": "tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", > + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings. Sample with: BR_MISP_RETIRED.ALL_BRANCHES", > + "ScaleUnit": "100%", > + "Unit": "cpu_core" > + }, > + { > + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due staying in C0.1 power-performance optimized state (Faster wakeup time; Smaller power savings).", > + "MetricExpr": "cpu_core@CPU_CLK_UNHALTED.C01@ / tma_info_thread_clks", > + "MetricGroup": "C0Wait;TopdownL4;tma_L4_group;tma_serializing_operation_group", > + "MetricName": "tma_c01_wait", > + "MetricThreshold": "tma_c01_wait > 0.05 & (tma_serializing_operation > 0.1 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", > + "ScaleUnit": "100%", > + "Unit": "cpu_core" > + }, > + { > + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due staying in C0.2 power-performance optimized state (Slower wakeup time; Larger power savings).", > + "MetricExpr": "cpu_core@CPU_CLK_UNHALTED.C02@ / tma_info_thread_clks", > + "MetricGroup": "C0Wait;TopdownL4;tma_L4_group;tma_serializing_operation_group", > + "MetricName": "tma_c02_wait", > + "MetricThreshold": "tma_c02_wait > 0.05 & (tma_serializing_operation > 0.1 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", > + "ScaleUnit": "100%", > + "Unit": "cpu_core" > + }, > + { > + "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction", > + "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)", > + "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group", > + "MetricName": "tma_cisc", > + "MetricThreshold": "tma_cisc > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1)", > + "PublicDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources. Sample with: FRONTEND_RETIRED.MS_FLOWS", > + "ScaleUnit": "100%", > + "Unit": "cpu_core" > + }, > + { > + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears", > + "MetricExpr": "(1 - tma_branch_mispredicts / tma_bad_speculation) * cpu_core@INT_MISC.CLEAR_RESTEER_CYCLES@ / tma_info_thread_clks", > + "MetricGroup": "BadSpec;MachineClears;TopdownL4;tma_L4_group;tma_branch_resteers_group;tma_issueMC", > + "MetricName": "tma_clears_resteers", > + "MetricThreshold": "tma_clears_resteers > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", > + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES. Related metrics: tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_ms_switches", > + "ScaleUnit": "100%", > + "Unit": "cpu_core" > + }, > + { > + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses", > + "MetricExpr": "(cpu_core@MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS@ * min(cpu_core@MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS@:retire_latency, 24 * tma_info_system_core_frequency) + cpu_core@MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD@ * min(cpu_core@MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD@:retire_latency, 25 * tma_info_system_core_frequency) * (cpu_core@OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM@ / (cpu_core@OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM@ + cpu_core@OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD@))) * (1 + cpu_core@MEM_LOAD_RETIRED.FB_HIT@ / cpu_core@MEM_LOAD_RETIRED.L1_MISS@ / 2) / tma_info_thread_clks", Thanks Weilin! The modifier on an event doesn't usually have the colon when there is a slash. So: cpu_core@MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD@:retire_latency Should be: cpu_core@MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD@retire_latency The modifiers also tend to be a single character. The modifier 'R' is unused, so I wonder we can use it here so that we can support these events not just in metrics. Ian ^ permalink raw reply [flat|nested] 10+ messages in thread
* RE: [RFC PATCH v2 6/6] perf vendor events intel: Add MTL metric json files 2024-02-28 16:50 ` Ian Rogers @ 2024-02-29 1:36 ` Wang, Weilin 2024-02-29 2:01 ` Ian Rogers 0 siblings, 1 reply; 10+ messages in thread From: Wang, Weilin @ 2024-02-29 1:36 UTC (permalink / raw) To: Ian Rogers Cc: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo, Alexander Shishkin, Jiri Olsa, Namhyung Kim, Hunter, Adrian, Kan Liang, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Taylor, Perry, Alt, Samantha, Biggers, Caleb > -----Original Message----- > From: Ian Rogers <irogers@google.com> > Sent: Wednesday, February 28, 2024 8:50 AM > To: Wang, Weilin <weilin.wang@intel.com> > Cc: Peter Zijlstra <peterz@infradead.org>; Ingo Molnar <mingo@redhat.com>; > Arnaldo Carvalho de Melo <acme@kernel.org>; Alexander Shishkin > <alexander.shishkin@linux.intel.com>; Jiri Olsa <jolsa@kernel.org>; Namhyung > Kim <namhyung@kernel.org>; Hunter, Adrian <adrian.hunter@intel.com>; > Kan Liang <kan.liang@linux.intel.com>; linux-perf-users@vger.kernel.org; > linux-kernel@vger.kernel.org; Taylor, Perry <perry.taylor@intel.com>; Alt, > Samantha <samantha.alt@intel.com>; Biggers, Caleb > <caleb.biggers@intel.com> > Subject: Re: [RFC PATCH v2 6/6] perf vendor events intel: Add MTL metric json > files > > On Wed, Feb 28, 2024 at 8:12 AM <weilin.wang@intel.com> wrote: > > > > From: Weilin Wang <weilin.wang@intel.com> > > > > Add MTL metric json file at TMA4.7 [1]. Some of the metrics' formulas use > TPEBS > > retire_latency in MTL. > > > > [1] https://lore.kernel.org/all/20240214011820.644458-1- > irogers@google.com/ > > > > Signed-off-by: Weilin Wang <weilin.wang@intel.com> > > --- > > .../arch/x86/meteorlake/metricgroups.json | 127 + > > .../arch/x86/meteorlake/mtl-metrics.json | 2531 +++++++++++++++++ > > 2 files changed, 2658 insertions(+) > > create mode 100644 tools/perf/pmu- > events/arch/x86/meteorlake/metricgroups.json > > create mode 100644 tools/perf/pmu-events/arch/x86/meteorlake/mtl- > metrics.json > > > > diff --git a/tools/perf/pmu-events/arch/x86/meteorlake/metricgroups.json > b/tools/perf/pmu-events/arch/x86/meteorlake/metricgroups.json > > new file mode 100644 > > index 000000000000..7a03835f262c > > --- /dev/null > > +++ b/tools/perf/pmu-events/arch/x86/meteorlake/metricgroups.json > > @@ -0,0 +1,127 @@ > > +{ > > + "Backend": "Grouping from Top-down Microarchitecture Analysis Metrics > spreadsheet", > > + "Bad": "Grouping from Top-down Microarchitecture Analysis Metrics > spreadsheet", > > + "BadSpec": "Grouping from Top-down Microarchitecture Analysis Metrics > spreadsheet", > > + "BigFootprint": "Grouping from Top-down Microarchitecture Analysis > Metrics spreadsheet", > > + "BrMispredicts": "Grouping from Top-down Microarchitecture Analysis > Metrics spreadsheet", > > + "Branches": "Grouping from Top-down Microarchitecture Analysis > Metrics spreadsheet", > > + "C0Wait": "Grouping from Top-down Microarchitecture Analysis Metrics > spreadsheet", > > + "CacheHits": "Grouping from Top-down Microarchitecture Analysis > Metrics spreadsheet", > > + "CodeGen": "Grouping from Top-down Microarchitecture Analysis > Metrics spreadsheet", > > + "Compute": "Grouping from Top-down Microarchitecture Analysis > Metrics spreadsheet", > > + "Cor": "Grouping from Top-down Microarchitecture Analysis Metrics > spreadsheet", > > + "DSB": "Grouping from Top-down Microarchitecture Analysis Metrics > spreadsheet", > > + "DSBmiss": "Grouping from Top-down Microarchitecture Analysis Metrics > spreadsheet", > > + "DataSharing": "Grouping from Top-down Microarchitecture Analysis > Metrics spreadsheet", > > + "Fed": "Grouping from Top-down Microarchitecture Analysis Metrics > spreadsheet", > > + "FetchBW": "Grouping from Top-down Microarchitecture Analysis > Metrics spreadsheet", > > + "FetchLat": "Grouping from Top-down Microarchitecture Analysis Metrics > spreadsheet", > > + "Flops": "Grouping from Top-down Microarchitecture Analysis Metrics > spreadsheet", > > + "FpScalar": "Grouping from Top-down Microarchitecture Analysis Metrics > spreadsheet", > > + "FpVector": "Grouping from Top-down Microarchitecture Analysis > Metrics spreadsheet", > > + "Frontend": "Grouping from Top-down Microarchitecture Analysis > Metrics spreadsheet", > > + "HPC": "Grouping from Top-down Microarchitecture Analysis Metrics > spreadsheet", > > + "IcMiss": "Grouping from Top-down Microarchitecture Analysis Metrics > spreadsheet", > > + "InsType": "Grouping from Top-down Microarchitecture Analysis Metrics > spreadsheet", > > + "IntVector": "Grouping from Top-down Microarchitecture Analysis > Metrics spreadsheet", > > + "L2Evicts": "Grouping from Top-down Microarchitecture Analysis Metrics > spreadsheet", > > + "LSD": "Grouping from Top-down Microarchitecture Analysis Metrics > spreadsheet", > > + "MachineClears": "Grouping from Top-down Microarchitecture Analysis > Metrics spreadsheet", > > + "Machine_Clears": "Grouping from Top-down Microarchitecture Analysis > Metrics spreadsheet", > > + "Mem": "Grouping from Top-down Microarchitecture Analysis Metrics > spreadsheet", > > + "MemOffcore": "Grouping from Top-down Microarchitecture Analysis > Metrics spreadsheet", > > + "MemoryBW": "Grouping from Top-down Microarchitecture Analysis > Metrics spreadsheet", > > + "MemoryBound": "Grouping from Top-down Microarchitecture Analysis > Metrics spreadsheet", > > + "MemoryLat": "Grouping from Top-down Microarchitecture Analysis > Metrics spreadsheet", > > + "MemoryTLB": "Grouping from Top-down Microarchitecture Analysis > Metrics spreadsheet", > > + "Memory_BW": "Grouping from Top-down Microarchitecture Analysis > Metrics spreadsheet", > > + "Memory_Lat": "Grouping from Top-down Microarchitecture Analysis > Metrics spreadsheet", > > + "MicroSeq": "Grouping from Top-down Microarchitecture Analysis > Metrics spreadsheet", > > + "OS": "Grouping from Top-down Microarchitecture Analysis Metrics > spreadsheet", > > + "Offcore": "Grouping from Top-down Microarchitecture Analysis Metrics > spreadsheet", > > + "PGO": "Grouping from Top-down Microarchitecture Analysis Metrics > spreadsheet", > > + "Pipeline": "Grouping from Top-down Microarchitecture Analysis Metrics > spreadsheet", > > + "PortsUtil": "Grouping from Top-down Microarchitecture Analysis Metrics > spreadsheet", > > + "Power": "Grouping from Top-down Microarchitecture Analysis Metrics > spreadsheet", > > + "Prefetches": "Grouping from Top-down Microarchitecture Analysis > Metrics spreadsheet", > > + "Ret": "Grouping from Top-down Microarchitecture Analysis Metrics > spreadsheet", > > + "Retire": "Grouping from Top-down Microarchitecture Analysis Metrics > spreadsheet", > > + "SMT": "Grouping from Top-down Microarchitecture Analysis Metrics > spreadsheet", > > + "Server": "Grouping from Top-down Microarchitecture Analysis Metrics > spreadsheet", > > + "Snoop": "Grouping from Top-down Microarchitecture Analysis Metrics > spreadsheet", > > + "SoC": "Grouping from Top-down Microarchitecture Analysis Metrics > spreadsheet", > > + "Summary": "Grouping from Top-down Microarchitecture Analysis > Metrics spreadsheet", > > + "TmaL1": "Grouping from Top-down Microarchitecture Analysis Metrics > spreadsheet", > > + "TmaL2": "Grouping from Top-down Microarchitecture Analysis Metrics > spreadsheet", > > + "TmaL3mem": "Grouping from Top-down Microarchitecture Analysis > Metrics spreadsheet", > > + "TopdownL1": "Metrics for top-down breakdown at level 1", > > + "TopdownL2": "Metrics for top-down breakdown at level 2", > > + "TopdownL3": "Metrics for top-down breakdown at level 3", > > + "TopdownL4": "Metrics for top-down breakdown at level 4", > > + "TopdownL5": "Metrics for top-down breakdown at level 5", > > + "TopdownL6": "Metrics for top-down breakdown at level 6", > > + "tma_L1_group": "Metrics for top-down breakdown at level 1", > > + "tma_L2_group": "Metrics for top-down breakdown at level 2", > > + "tma_L3_group": "Metrics for top-down breakdown at level 3", > > + "tma_L4_group": "Metrics for top-down breakdown at level 4", > > + "tma_L5_group": "Metrics for top-down breakdown at level 5", > > + "tma_L6_group": "Metrics for top-down breakdown at level 6", > > + "tma_alu_op_utilization_group": "Metrics contributing to > tma_alu_op_utilization category", > > + "tma_assists_group": "Metrics contributing to tma_assists category", > > + "tma_backend_bound_aux_group": "Metrics contributing to > tma_backend_bound_aux category", > > + "tma_backend_bound_group": "Metrics contributing to > tma_backend_bound category", > > + "tma_bad_speculation_group": "Metrics contributing to > tma_bad_speculation category", > > + "tma_base_group": "Metrics contributing to tma_base category", > > + "tma_branch_mispredicts_group": "Metrics contributing to > tma_branch_mispredicts category", > > + "tma_branch_resteers_group": "Metrics contributing to > tma_branch_resteers category", > > + "tma_core_bound_group": "Metrics contributing to tma_core_bound > category", > > + "tma_dram_bound_group": "Metrics contributing to tma_dram_bound > category", > > + "tma_dtlb_load_group": "Metrics contributing to tma_dtlb_load > category", > > + "tma_dtlb_store_group": "Metrics contributing to tma_dtlb_store > category", > > + "tma_fetch_bandwidth_group": "Metrics contributing to > tma_fetch_bandwidth category", > > + "tma_fetch_latency_group": "Metrics contributing to tma_fetch_latency > category", > > + "tma_fp_arith_group": "Metrics contributing to tma_fp_arith category", > > + "tma_fp_vector_group": "Metrics contributing to tma_fp_vector > category", > > + "tma_frontend_bound_group": "Metrics contributing to > tma_frontend_bound category", > > + "tma_heavy_operations_group": "Metrics contributing to > tma_heavy_operations category", > > + "tma_int_operations_group": "Metrics contributing to > tma_int_operations category", > > + "tma_issue2P": "Metrics related by the issue $issue2P", > > + "tma_issueBM": "Metrics related by the issue $issueBM", > > + "tma_issueBW": "Metrics related by the issue $issueBW", > > + "tma_issueComp": "Metrics related by the issue $issueComp", > > + "tma_issueD0": "Metrics related by the issue $issueD0", > > + "tma_issueFB": "Metrics related by the issue $issueFB", > > + "tma_issueFL": "Metrics related by the issue $issueFL", > > + "tma_issueL1": "Metrics related by the issue $issueL1", > > + "tma_issueLat": "Metrics related by the issue $issueLat", > > + "tma_issueMC": "Metrics related by the issue $issueMC", > > + "tma_issueMS": "Metrics related by the issue $issueMS", > > + "tma_issueMV": "Metrics related by the issue $issueMV", > > + "tma_issueRFO": "Metrics related by the issue $issueRFO", > > + "tma_issueSL": "Metrics related by the issue $issueSL", > > + "tma_issueSO": "Metrics related by the issue $issueSO", > > + "tma_issueSmSt": "Metrics related by the issue $issueSmSt", > > + "tma_issueSpSt": "Metrics related by the issue $issueSpSt", > > + "tma_issueSyncxn": "Metrics related by the issue $issueSyncxn", > > + "tma_issueTLB": "Metrics related by the issue $issueTLB", > > + "tma_l1_bound_group": "Metrics contributing to tma_l1_bound > category", > > + "tma_l3_bound_group": "Metrics contributing to tma_l3_bound > category", > > + "tma_light_operations_group": "Metrics contributing to > tma_light_operations category", > > + "tma_load_op_utilization_group": "Metrics contributing to > tma_load_op_utilization category", > > + "tma_machine_clears_group": "Metrics contributing to > tma_machine_clears category", > > + "tma_mem_latency_group": "Metrics contributing to tma_mem_latency > category", > > + "tma_mem_scheduler_group": "Metrics contributing to > tma_mem_scheduler category", > > + "tma_memory_bound_group": "Metrics contributing to > tma_memory_bound category", > > + "tma_microcode_sequencer_group": "Metrics contributing to > tma_microcode_sequencer category", > > + "tma_mite_group": "Metrics contributing to tma_mite category", > > + "tma_nuke_group": "Metrics contributing to tma_nuke category", > > + "tma_other_light_ops_group": "Metrics contributing to > tma_other_light_ops category", > > + "tma_ports_utilization_group": "Metrics contributing to > tma_ports_utilization category", > > + "tma_ports_utilized_0_group": "Metrics contributing to > tma_ports_utilized_0 category", > > + "tma_ports_utilized_3m_group": "Metrics contributing to > tma_ports_utilized_3m category", > > + "tma_resource_bound_group": "Metrics contributing to > tma_resource_bound category", > > + "tma_retiring_group": "Metrics contributing to tma_retiring category", > > + "tma_serializing_operation_group": "Metrics contributing to > tma_serializing_operation category", > > + "tma_store_bound_group": "Metrics contributing to tma_store_bound > category", > > + "tma_store_op_utilization_group": "Metrics contributing to > tma_store_op_utilization category" > > +} > > diff --git a/tools/perf/pmu-events/arch/x86/meteorlake/mtl-metrics.json > b/tools/perf/pmu-events/arch/x86/meteorlake/mtl-metrics.json > > new file mode 100644 > > index 000000000000..12df19538fd6 > > --- /dev/null > > +++ b/tools/perf/pmu-events/arch/x86/meteorlake/mtl-metrics.json > > @@ -0,0 +1,2531 @@ > > +[ > > + { > > + "BriefDescription": "C10 residency percent per package", > > + "MetricExpr": "cstate_pkg@c10\\-residency@ / TSC", > > + "MetricGroup": "Power", > > + "MetricName": "C10_Pkg_Residency", > > + "ScaleUnit": "100%" > > + }, > > + { > > + "BriefDescription": "C1 residency percent per core", > > + "MetricExpr": "cstate_core@c1\\-residency@ / TSC", > > + "MetricGroup": "Power", > > + "MetricName": "C1_Core_Residency", > > + "ScaleUnit": "100%" > > + }, > > + { > > + "BriefDescription": "C2 residency percent per package", > > + "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC", > > + "MetricGroup": "Power", > > + "MetricName": "C2_Pkg_Residency", > > + "ScaleUnit": "100%" > > + }, > > + { > > + "BriefDescription": "C3 residency percent per package", > > + "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC", > > + "MetricGroup": "Power", > > + "MetricName": "C3_Pkg_Residency", > > + "ScaleUnit": "100%" > > + }, > > + { > > + "BriefDescription": "C6 residency percent per core", > > + "MetricExpr": "cstate_core@c6\\-residency@ / TSC", > > + "MetricGroup": "Power", > > + "MetricName": "C6_Core_Residency", > > + "ScaleUnit": "100%" > > + }, > > + { > > + "BriefDescription": "C6 residency percent per package", > > + "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC", > > + "MetricGroup": "Power", > > + "MetricName": "C6_Pkg_Residency", > > + "ScaleUnit": "100%" > > + }, > > + { > > + "BriefDescription": "C7 residency percent per core", > > + "MetricExpr": "cstate_core@c7\\-residency@ / TSC", > > + "MetricGroup": "Power", > > + "MetricName": "C7_Core_Residency", > > + "ScaleUnit": "100%" > > + }, > > + { > > + "BriefDescription": "C7 residency percent per package", > > + "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC", > > + "MetricGroup": "Power", > > + "MetricName": "C7_Pkg_Residency", > > + "ScaleUnit": "100%" > > + }, > > + { > > + "BriefDescription": "C8 residency percent per package", > > + "MetricExpr": "cstate_pkg@c8\\-residency@ / TSC", > > + "MetricGroup": "Power", > > + "MetricName": "C8_Pkg_Residency", > > + "ScaleUnit": "100%" > > + }, > > + { > > + "BriefDescription": "C9 residency percent per package", > > + "MetricExpr": "cstate_pkg@c9\\-residency@ / TSC", > > + "MetricGroup": "Power", > > + "MetricName": "C9_Pkg_Residency", > > + "ScaleUnit": "100%" > > + }, > > + { > > + "BriefDescription": "Percentage of cycles spent in System Management > Interrupts.", > > + "MetricExpr": "((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > > 0 else 0)", > > + "MetricGroup": "smi", > > + "MetricName": "smi_cycles", > > + "MetricThreshold": "smi_cycles > 0.1", > > + "ScaleUnit": "100%" > > + }, > > + { > > + "BriefDescription": "Number of SMI interrupts.", > > + "MetricExpr": "msr@smi@", > > + "MetricGroup": "smi", > > + "MetricName": "smi_num", > > + "ScaleUnit": "1SMI#" > > + }, > > + { > > + "BriefDescription": "Counts the number of issue slots that were not > consumed by the backend due to certain allocation restrictions.", > > + "MetricExpr": > "cpu_atom@TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS@ / > tma_info_core_slots", > > + "MetricGroup": > "TopdownL3;tma_L3_group;tma_resource_bound_group", > > + "MetricName": "tma_alloc_restriction", > > + "MetricThreshold": "tma_alloc_restriction > 0.1", > > + "ScaleUnit": "100%", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Counts the total number of issue slots that were > not consumed by the backend due to backend stalls", > > + "MetricExpr": "cpu_atom@TOPDOWN_BE_BOUND.ALL@ / > tma_info_core_slots", > > + "MetricGroup": "TopdownL1;tma_L1_group", > > + "MetricName": "tma_backend_bound", > > + "MetricThreshold": "tma_backend_bound > 0.1", > > + "MetricgroupNoGroup": "TopdownL1", > > + "PublicDescription": "Counts the total number of issue slots that were > not consumed by the backend due to backend stalls. Note that uops must be > available for consumption in order for this event to count. If a uop is not > available (IQ is empty), this event will not count. The rest of these subevents > count backend stalls, in cycles, due to an outstanding request which is > memory bound vs core bound. The subevents are not slot based events and > therefore can not be precisely added or subtracted from the > Backend_Bound_Aux subevents which are slot based.", > > + "ScaleUnit": "100%", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Counts the total number of issue slots that were > not consumed by the backend due to backend stalls", > > + "MetricExpr": "tma_backend_bound", > > + "MetricGroup": "TopdownL1;tma_L1_group", > > + "MetricName": "tma_backend_bound_aux", > > + "MetricThreshold": "tma_backend_bound_aux > 0.2", > > + "MetricgroupNoGroup": "TopdownL1", > > + "PublicDescription": "Counts the total number of issue slots that were > not consumed by the backend due to backend stalls. Note that UOPS must be > available for consumption in order for this event to count. If a uop is not > available (IQ is empty), this event will not count. All of these subevents count > backend stalls, in slots, due to a resource limitation. These are not cycle based > events and therefore can not be precisely added or subtracted from the > Backend_Bound subevents which are cycle based. These subevents are > supplementary to Backend_Bound and can be used to analyze results from a > resource perspective at allocation.", > > + "ScaleUnit": "100%", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Counts the total number of issue slots that were > not consumed by the backend because allocation is stalled due to a > mispredicted jump or a machine clear", > > + "MetricExpr": "cpu_atom@TOPDOWN_BAD_SPECULATION.ALL@ / > tma_info_core_slots", > > + "MetricGroup": "TopdownL1;tma_L1_group", > > + "MetricName": "tma_bad_speculation", > > + "MetricThreshold": "tma_bad_speculation > 0.15", > > + "MetricgroupNoGroup": "TopdownL1", > > + "PublicDescription": "Counts the total number of issue slots that were > not consumed by the backend because allocation is stalled due to a > mispredicted jump or a machine clear. Only issue slots wasted due to fast > nukes such as memory ordering nukes are counted. Other nukes are not > accounted for. Counts all issue slots blocked during this recovery window > including relevant microcode flows and while uops are not yet available in the > instruction queue (IQ). Also includes the issue slots that were consumed by > the backend but were thrown away because they were younger than the > mispredict or machine clear.", > > + "ScaleUnit": "100%", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Counts the number of uops that are not from the > microsequencer.", > > + "MetricExpr": "(cpu_atom@TOPDOWN_RETIRING.ALL@ - > cpu_atom@UOPS_RETIRED.MS@) / tma_info_core_slots", > > + "MetricGroup": "TopdownL2;tma_L2_group;tma_retiring_group", > > + "MetricName": "tma_base", > > + "MetricThreshold": "tma_base > 0.6", > > + "MetricgroupNoGroup": "TopdownL2", > > + "ScaleUnit": "100%", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Counts the number of issue slots that were not > delivered by the frontend due to BACLEARS, which occurs when the Branch > Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch > predictor in the frontend", > > + "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.BRANCH_DETECT@ > / tma_info_core_slots", > > + "MetricGroup": > "TopdownL3;tma_L3_group;tma_fetch_latency_group", > > + "MetricName": "tma_branch_detect", > > + "MetricThreshold": "tma_branch_detect > 0.05", > > + "PublicDescription": "Counts the number of issue slots that were not > delivered by the frontend due to BACLEARS, which occurs when the Branch > Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch > predictor in the frontend. Includes BACLEARS due to all branch types including > conditional and unconditional jumps, returns, and indirect branches.", > > + "ScaleUnit": "100%", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Counts the number of issue slots that were not > consumed by the backend due to branch mispredicts.", > > + "MetricExpr": > "cpu_atom@TOPDOWN_BAD_SPECULATION.MISPREDICT@ / > tma_info_core_slots", > > + "MetricGroup": > "TopdownL2;tma_L2_group;tma_bad_speculation_group", > > + "MetricName": "tma_branch_mispredicts", > > + "MetricThreshold": "tma_branch_mispredicts > 0.05", > > + "MetricgroupNoGroup": "TopdownL2", > > + "ScaleUnit": "100%", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Counts the number of issue slots that were not > delivered by the frontend due to BTCLEARS, which occurs when the Branch > Target Buffer (BTB) predicts a taken branch.", > > + "MetricExpr": > "cpu_atom@TOPDOWN_FE_BOUND.BRANCH_RESTEER@ / > tma_info_core_slots", > > + "MetricGroup": > "TopdownL3;tma_L3_group;tma_fetch_latency_group", > > + "MetricName": "tma_branch_resteer", > > + "MetricThreshold": "tma_branch_resteer > 0.05", > > + "ScaleUnit": "100%", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Counts the number of issue slots that were not > delivered by the frontend due to the microcode sequencer (MS).", > > + "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.CISC@ / > tma_info_core_slots", > > + "MetricGroup": > "TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", > > + "MetricName": "tma_cisc", > > + "MetricThreshold": "tma_cisc > 0.05", > > + "ScaleUnit": "100%", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Counts the number of cycles due to backend > bound stalls that are core execution bound and not attributed to outstanding > demand load or store stalls.", > > + "MetricExpr": "max(0, tma_backend_bound - tma_memory_bound)", > > + "MetricGroup": > "TopdownL2;tma_L2_group;tma_backend_bound_group", > > + "MetricName": "tma_core_bound", > > + "MetricThreshold": "tma_core_bound > 0.1", > > + "MetricgroupNoGroup": "TopdownL2", > > + "ScaleUnit": "100%", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Counts the number of issue slots that were not > delivered by the frontend due to decode stalls.", > > + "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.DECODE@ / > tma_info_core_slots", > > + "MetricGroup": > "TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", > > + "MetricName": "tma_decode", > > + "MetricThreshold": "tma_decode > 0.05", > > + "ScaleUnit": "100%", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Counts the number of machine clears relative to > the number of nuke slots due to memory disambiguation.", > > + "MetricExpr": "tma_nuke * > (cpu_atom@MACHINE_CLEARS.DISAMBIGUATION@ / > cpu_atom@MACHINE_CLEARS.SLOW@)", > > + "MetricGroup": "TopdownL4;tma_L4_group;tma_nuke_group", > > + "MetricName": "tma_disambiguation", > > + "MetricThreshold": "tma_disambiguation > 0.02", > > + "ScaleUnit": "100%", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Counts the number of cycles the core is stalled due > to a demand load miss which hit in DRAM or MMIO (Non-DRAM).", > > + "MetricExpr": "cpu_atom@MEM_BOUND_STALLS_LOAD.LLC_MISS@ / > tma_info_core_clks - max((cpu_atom@MEM_BOUND_STALLS_LOAD.ALL@ - > cpu_atom@LD_HEAD.L1_MISS_AT_RET@) / tma_info_core_clks, 0) * > cpu_atom@MEM_BOUND_STALLS_LOAD.LLC_MISS@ / > cpu_atom@MEM_BOUND_STALLS_LOAD.ALL@", > > + "MetricGroup": > "TopdownL3;tma_L3_group;tma_memory_bound_group", > > + "MetricName": "tma_dram_bound", > > + "MetricThreshold": "tma_dram_bound > 0.1", > > + "ScaleUnit": "100%", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Counts the number of issue slots that were not > consumed by the backend due to a machine clear classified as a fast nuke due > to memory ordering, memory disambiguation and memory renaming.", > > + "MetricExpr": > "cpu_atom@TOPDOWN_BAD_SPECULATION.FASTNUKE@ / > tma_info_core_slots", > > + "MetricGroup": > "TopdownL3;tma_L3_group;tma_machine_clears_group", > > + "MetricName": "tma_fast_nuke", > > + "MetricThreshold": "tma_fast_nuke > 0.05", > > + "ScaleUnit": "100%", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Counts the number of issue slots that were not > delivered by the frontend due to frontend bandwidth restrictions due to > decode, predecode, cisc, and other limitations.", > > + "MetricExpr": > "cpu_atom@TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH@ / > tma_info_core_slots", > > + "MetricGroup": > "TopdownL2;tma_L2_group;tma_frontend_bound_group", > > + "MetricName": "tma_fetch_bandwidth", > > + "MetricThreshold": "tma_fetch_bandwidth > 0.1", > > + "MetricgroupNoGroup": "TopdownL2", > > + "ScaleUnit": "100%", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Counts the number of issue slots that were not > delivered by the frontend due to frontend bandwidth restrictions due to > decode, predecode, cisc, and other limitations.", > > + "MetricExpr": > "cpu_atom@TOPDOWN_FE_BOUND.FRONTEND_LATENCY@ / > tma_info_core_slots", > > + "MetricGroup": > "TopdownL2;tma_L2_group;tma_frontend_bound_group", > > + "MetricName": "tma_fetch_latency", > > + "MetricThreshold": "tma_fetch_latency > 0.15", > > + "MetricgroupNoGroup": "TopdownL2", > > + "ScaleUnit": "100%", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Counts the number of machine clears relative to > the number of nuke slots due to FP assists.", > > + "MetricExpr": "tma_nuke * > (cpu_atom@MACHINE_CLEARS.FP_ASSIST@ / > cpu_atom@MACHINE_CLEARS.SLOW@)", > > + "MetricGroup": "TopdownL4;tma_L4_group;tma_nuke_group", > > + "MetricName": "tma_fp_assist", > > + "MetricThreshold": "tma_fp_assist > 0.02", > > + "ScaleUnit": "100%", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Counts the number of floating point divide > operations per uop.", > > + "MetricExpr": "cpu_atom@UOPS_RETIRED.FPDIV@ / > tma_info_core_slots", > > + "MetricGroup": "TopdownL3;tma_L3_group;tma_base_group", > > + "MetricName": "tma_fpdiv_uops", > > + "MetricThreshold": "tma_fpdiv_uops > 0.2", > > + "ScaleUnit": "100%", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Counts the number of issue slots that were not > consumed by the backend due to frontend stalls.", > > + "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.ALL@ / > tma_info_core_slots", > > + "MetricGroup": "TopdownL1;tma_L1_group", > > + "MetricName": "tma_frontend_bound", > > + "MetricThreshold": "tma_frontend_bound > 0.2", > > + "MetricgroupNoGroup": "TopdownL1", > > + "ScaleUnit": "100%", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Counts the number of issue slots that were not > delivered by the frontend due to instruction cache misses.", > > + "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.ICACHE@ / > tma_info_core_slots", > > + "MetricGroup": > "TopdownL3;tma_L3_group;tma_fetch_latency_group", > > + "MetricName": "tma_icache_misses", > > + "MetricThreshold": "tma_icache_misses > 0.05", > > + "ScaleUnit": "100%", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "", > > + "MetricExpr": "cpu_atom@CPU_CLK_UNHALTED.CORE@", > > + "MetricName": "tma_info_core_clks", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "", > > + "MetricExpr": "cpu_atom@CPU_CLK_UNHALTED.CORE_P@", > > + "MetricName": "tma_info_core_clks_p", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Cycles Per Instruction", > > + "MetricExpr": "tma_info_core_clks / INST_RETIRED.ANY", > > + "MetricName": "tma_info_core_cpi", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Instructions Per Cycle", > > + "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / > tma_info_core_clks", > > + "MetricName": "tma_info_core_ipc", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "", > > + "MetricExpr": "6 * tma_info_core_clks", > > + "MetricName": "tma_info_core_slots", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Uops Per Instruction", > > + "MetricExpr": "cpu_atom@UOPS_RETIRED.ALL@ / > INST_RETIRED.ANY", > > + "MetricName": "tma_info_core_upi", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Percent of instruction miss cost that hit in DRAM", > > + "MetricExpr": "100 * > cpu_atom@MEM_BOUND_STALLS_IFETCH.LLC_MISS@ / > cpu_atom@MEM_BOUND_STALLS_IFETCH.ALL@", > > + "MetricName": "tma_info_frontend_inst_miss_cost_dramhit_percent", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Percent of instruction miss cost that hit in the L2", > > + "MetricExpr": "100 * > cpu_atom@MEM_BOUND_STALLS_IFETCH.L2_HIT@ / > cpu_atom@MEM_BOUND_STALLS_IFETCH.ALL@", > > + "MetricName": "tma_info_frontend_inst_miss_cost_l2hit_percent", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Percent of instruction miss cost that hit in the L3", > > + "MetricExpr": "100 * > cpu_atom@MEM_BOUND_STALLS_IFETCH.LLC_HIT@ / > cpu_atom@MEM_BOUND_STALLS_IFETCH.ALL@", > > + "MetricName": "tma_info_frontend_inst_miss_cost_l3hit_percent", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Ratio of all branches which mispredict", > > + "MetricExpr": "cpu_atom@BR_MISP_RETIRED.ALL_BRANCHES@ / > BR_INST_RETIRED.ALL_BRANCHES", > > + "MetricName": "tma_info_inst_mix_branch_mispredict_ratio", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Ratio between Mispredicted branches and > unknown branches", > > + "MetricExpr": "cpu_atom@BR_MISP_RETIRED.ALL_BRANCHES@ / > BACLEARS.ANY", > > + "MetricName": > "tma_info_inst_mix_branch_mispredict_to_unknown_branch_ratio", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Percentage of all uops which are FPDiv uops", > > + "MetricExpr": "100 * cpu_atom@UOPS_RETIRED.FPDIV@ / > UOPS_RETIRED.ALL", > > + "MetricName": "tma_info_inst_mix_fpdiv_uop_ratio", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Percentage of all uops which are IDiv uops", > > + "MetricExpr": "100 * cpu_atom@UOPS_RETIRED.IDIV@ / > UOPS_RETIRED.ALL", > > + "MetricName": "tma_info_inst_mix_idiv_uop_ratio", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Instructions per Branch (lower number means > higher occurrence rate)", > > + "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / > BR_INST_RETIRED.ALL_BRANCHES", > > + "MetricName": "tma_info_inst_mix_ipbranch", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Instruction per (near) call (lower number means > higher occurrence rate)", > > + "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / > BR_INST_RETIRED.NEAR_CALL", > > + "MetricName": "tma_info_inst_mix_ipcall", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Instructions per Far Branch", > > + "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / > (cpu_atom@BR_INST_RETIRED.FAR_BRANCH@ / 2)", > > + "MetricName": "tma_info_inst_mix_ipfarbranch", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Instructions per Load", > > + "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / > MEM_UOPS_RETIRED.ALL_LOADS", > > + "MetricName": "tma_info_inst_mix_ipload", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Instructions per retired conditional Branch > Misprediction where the branch was not taken", > > + "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / > (cpu_atom@BR_MISP_RETIRED.COND@ - > cpu_atom@BR_MISP_RETIRED.COND_TAKEN@)", > > + "MetricName": "tma_info_inst_mix_ipmisp_cond_ntaken", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Instructions per retired conditional Branch > Misprediction where the branch was taken", > > + "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / > BR_MISP_RETIRED.COND_TAKEN", > > + "MetricName": "tma_info_inst_mix_ipmisp_cond_taken", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Instructions per retired indirect call or jump Branch > Misprediction", > > + "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / > BR_MISP_RETIRED.INDIRECT", > > + "MetricName": "tma_info_inst_mix_ipmisp_indirect", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Instructions per retired return Branch > Misprediction", > > + "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / > BR_MISP_RETIRED.RETURN", > > + "MetricName": "tma_info_inst_mix_ipmisp_ret", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Instructions per retired Branch Misprediction", > > + "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / > BR_MISP_RETIRED.ALL_BRANCHES", > > + "MetricName": "tma_info_inst_mix_ipmispredict", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Instructions per Store", > > + "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / > MEM_UOPS_RETIRED.ALL_STORES", > > + "MetricName": "tma_info_inst_mix_ipstore", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Percentage of all uops which are ucode ops", > > + "MetricExpr": "100 * cpu_atom@UOPS_RETIRED.MS@ / > UOPS_RETIRED.ALL", > > + "MetricName": "tma_info_inst_mix_microcode_uop_ratio", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Percentage of all uops which are x87 uops", > > + "MetricExpr": "100 * cpu_atom@UOPS_RETIRED.X87@ / > UOPS_RETIRED.ALL", > > + "MetricName": "tma_info_inst_mix_x87_uop_ratio", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Percentage of total non-speculative loads with a > address aliasing block", > > + "MetricExpr": "100 * cpu_atom@LD_BLOCKS.ADDRESS_ALIAS@ / > MEM_UOPS_RETIRED.ALL_LOADS", > > + "MetricName": "tma_info_l1_bound_address_alias_blocks", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Percentage of total non-speculative loads that are > splits", > > + "MetricExpr": "100 * > cpu_atom@MEM_UOPS_RETIRED.SPLIT_LOADS@ / > MEM_UOPS_RETIRED.ALL_LOADS", > > + "MetricName": "tma_info_l1_bound_load_splits", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Percentage of total non-speculative loads with a > store forward or unknown store address block", > > + "MetricExpr": "100 * cpu_atom@LD_BLOCKS.DATA_UNKNOWN@ / > MEM_UOPS_RETIRED.ALL_LOADS", > > + "MetricName": "tma_info_l1_bound_store_fwd_blocks", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Cycle cost per L2 hit", > > + "MetricExpr": "cpu_atom@MEM_BOUND_STALLS_LOAD.L2_HIT@ / > MEM_LOAD_UOPS_RETIRED.L2_HIT", > > + "MetricName": "tma_info_memory_cycles_per_demand_load_l2_hit", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Cycle cost per LLC hit", > > + "MetricExpr": "cpu_atom@MEM_BOUND_STALLS_LOAD.LLC_HIT@ / > MEM_LOAD_UOPS_RETIRED.L3_HIT", > > + "MetricName": "tma_info_memory_cycles_per_demand_load_l3_hit", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "load ops retired per 1000 instruction", > > + "MetricExpr": "1e3 * cpu_atom@MEM_UOPS_RETIRED.ALL_LOADS@ / > INST_RETIRED.ANY", > > + "MetricName": "tma_info_memory_memloadpki", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Average CPU Utilization", > > + "MetricExpr": "cpu_atom@CPU_CLK_UNHALTED.REF_TSC@ / TSC", > > + "MetricName": "tma_info_system_cpu_utilization", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Fraction of cycles spent in Kernel mode", > > + "MetricExpr": "cpu_atom@CPU_CLK_UNHALTED.CORE@k / > CPU_CLK_UNHALTED.CORE", > > + "MetricGroup": "Summary", > > + "MetricName": "tma_info_system_kernel_utilization", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Average Frequency Utilization relative nominal > frequency", > > + "MetricExpr": "tma_info_core_clks / CPU_CLK_UNHALTED.REF_TSC", > > + "MetricGroup": "Power", > > + "MetricName": "tma_info_system_turbo_utilization", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Counts the number of issue slots that were not > delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) > misses.", > > + "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.ITLB_MISS@ / > tma_info_core_slots", > > + "MetricGroup": > "TopdownL3;tma_L3_group;tma_fetch_latency_group", > > + "MetricName": "tma_itlb_misses", > > + "MetricThreshold": "tma_itlb_misses > 0.05", > > + "ScaleUnit": "100%", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Counts the number of cycles that the oldest load of > the load buffer is stalled at retirement due to a load block.", > > + "MetricExpr": "cpu_atom@LD_HEAD.L1_BOUND_AT_RET@ / > tma_info_core_clks", > > + "MetricGroup": > "TopdownL3;tma_L3_group;tma_memory_bound_group", > > + "MetricName": "tma_l1_bound", > > + "MetricThreshold": "tma_l1_bound > 0.1", > > + "ScaleUnit": "100%", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Counts the number of cycles a core is stalled due to > a demand load which hit in the L2 Cache.", > > + "MetricExpr": "cpu_atom@MEM_BOUND_STALLS_LOAD.L2_HIT@ / > tma_info_core_clks - max((cpu_atom@MEM_BOUND_STALLS_LOAD.ALL@ - > cpu_atom@LD_HEAD.L1_MISS_AT_RET@) / tma_info_core_clks, 0) * > cpu_atom@MEM_BOUND_STALLS_LOAD.L2_HIT@ / > cpu_atom@MEM_BOUND_STALLS_LOAD.ALL@", > > + "MetricGroup": > "TopdownL3;tma_L3_group;tma_memory_bound_group", > > + "MetricName": "tma_l2_bound", > > + "MetricThreshold": "tma_l2_bound > 0.1", > > + "ScaleUnit": "100%", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Counts the number of cycles a core is stalled due to > a demand load which hit in the Last Level Cache (LLC) or other core with > HITE/F/M.", > > + "MetricExpr": "cpu_atom@MEM_BOUND_STALLS_LOAD.LLC_HIT@ / > tma_info_core_clks - max((cpu_atom@MEM_BOUND_STALLS_LOAD.ALL@ - > cpu_atom@LD_HEAD.L1_MISS_AT_RET@) / tma_info_core_clks, 0) * > cpu_atom@MEM_BOUND_STALLS_LOAD.LLC_HIT@ / > cpu_atom@MEM_BOUND_STALLS_LOAD.ALL@", > > + "MetricGroup": > "TopdownL3;tma_L3_group;tma_memory_bound_group", > > + "MetricName": "tma_l3_bound", > > + "MetricThreshold": "tma_l3_bound > 0.1", > > + "ScaleUnit": "100%", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Counts the number of cycles, relative to the > number of mem_scheduler slots, in which uops are blocked due to load buffer > full", > > + "MetricExpr": "tma_mem_scheduler * > cpu_atom@MEM_SCHEDULER_BLOCK.LD_BUF@ / > MEM_SCHEDULER_BLOCK.ALL", > > + "MetricGroup": > "TopdownL4;tma_L4_group;tma_mem_scheduler_group", > > + "MetricName": "tma_ld_buffer", > > + "MetricThreshold": "tma_ld_buffer > 0.05", > > + "ScaleUnit": "100%", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Counts the total number of issue slots that were > not consumed by the backend because allocation is stalled due to a machine > clear (nuke) of any kind including memory ordering and memory > disambiguation.", > > + "MetricExpr": > "cpu_atom@TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS@ / > tma_info_core_slots", > > + "MetricGroup": > "TopdownL2;tma_L2_group;tma_bad_speculation_group", > > + "MetricName": "tma_machine_clears", > > + "MetricThreshold": "tma_machine_clears > 0.05", > > + "MetricgroupNoGroup": "TopdownL2", > > + "ScaleUnit": "100%", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Counts the number of issue slots that were not > consumed by the backend due to memory reservation stalls in which a > scheduler is not able to accept uops.", > > + "MetricExpr": > "cpu_atom@TOPDOWN_BE_BOUND.MEM_SCHEDULER@ / > tma_info_core_slots", > > + "MetricGroup": > "TopdownL3;tma_L3_group;tma_resource_bound_group", > > + "MetricName": "tma_mem_scheduler", > > + "MetricThreshold": "tma_mem_scheduler > 0.1", > > + "ScaleUnit": "100%", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Counts the number of cycles the core is stalled due > to stores or loads.", > > + "MetricExpr": "min(tma_backend_bound, > cpu_atom@LD_HEAD.ANY_AT_RET@ / tma_info_core_clks + > tma_store_bound)", > > + "MetricGroup": > "TopdownL2;tma_L2_group;tma_backend_bound_group", > > + "MetricName": "tma_memory_bound", > > + "MetricThreshold": "tma_memory_bound > 0.2", > > + "MetricgroupNoGroup": "TopdownL2", > > + "ScaleUnit": "100%", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Counts the number of machine clears relative to > the number of nuke slots due to memory ordering.", > > + "MetricExpr": "tma_nuke * > (cpu_atom@MACHINE_CLEARS.MEMORY_ORDERING@ / > cpu_atom@MACHINE_CLEARS.SLOW@)", > > + "MetricGroup": "TopdownL4;tma_L4_group;tma_nuke_group", > > + "MetricName": "tma_memory_ordering", > > + "MetricThreshold": "tma_memory_ordering > 0.02", > > + "ScaleUnit": "100%", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Counts the number of uops that are from the > complex flows issued by the micro-sequencer (MS)", > > + "MetricExpr": "cpu_atom@UOPS_RETIRED.MS@ / > tma_info_core_slots", > > + "MetricGroup": "TopdownL2;tma_L2_group;tma_retiring_group", > > + "MetricName": "tma_ms_uops", > > + "MetricThreshold": "tma_ms_uops > 0.05", > > + "MetricgroupNoGroup": "TopdownL2", > > + "PublicDescription": "Counts the number of uops that are from the > complex flows issued by the micro-sequencer (MS). This includes uops from > flows due to complex instructions, faults, assists, and inserted flows.", > > + "ScaleUnit": "100%", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Counts the number of issue slots that were not > consumed by the backend due to IEC or FPC RAT stalls, which can be due to > FIQ or IEC reservation stalls in which the integer, floating point or SIMD > scheduler is not able to accept uops.", > > + "MetricExpr": > "cpu_atom@TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER@ / > tma_info_core_slots", > > + "MetricGroup": > "TopdownL3;tma_L3_group;tma_resource_bound_group", > > + "MetricName": "tma_non_mem_scheduler", > > + "MetricThreshold": "tma_non_mem_scheduler > 0.1", > > + "ScaleUnit": "100%", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Counts the number of issue slots that were not > consumed by the backend due to a machine clear (slow nuke).", > > + "MetricExpr": "cpu_atom@TOPDOWN_BAD_SPECULATION.NUKE@ / > tma_info_core_slots", > > + "MetricGroup": > "TopdownL3;tma_L3_group;tma_machine_clears_group", > > + "MetricName": "tma_nuke", > > + "MetricThreshold": "tma_nuke > 0.05", > > + "ScaleUnit": "100%", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Counts the number of issue slots that were not > delivered by the frontend due to other common frontend stalls not > categorized.", > > + "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.OTHER@ / > tma_info_core_slots", > > + "MetricGroup": > "TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", > > + "MetricName": "tma_other_fb", > > + "MetricThreshold": "tma_other_fb > 0.05", > > + "ScaleUnit": "100%", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Counts the number of cycles that the oldest load of > the load buffer is stalled at retirement due to a number of other load blocks.", > > + "MetricExpr": "cpu_atom@LD_HEAD.OTHER_AT_RET@ / > tma_info_core_clks", > > + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", > > + "MetricName": "tma_other_l1", > > + "MetricThreshold": "tma_other_l1 > 0.05", > > + "ScaleUnit": "100%", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Counts the number of cycles the core is stalled due > to a demand load miss which hits in the L2, LLC, DRAM or MMIO (Non-DRAM) > but could not be correctly attributed or cycles in which the load miss is waiting > on a request buffer.", > > + "MetricExpr": "max(0, tma_memory_bound - (tma_store_bound + > tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound))", > > + "MetricGroup": > "TopdownL3;tma_L3_group;tma_memory_bound_group", > > + "MetricName": "tma_other_load_store", > > + "MetricThreshold": "tma_other_load_store > 0.1", > > + "ScaleUnit": "100%", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Counts the number of uops retired excluding ms > and fp div uops.", > > + "MetricExpr": "(cpu_atom@TOPDOWN_RETIRING.ALL@ - > cpu_atom@UOPS_RETIRED.MS@ - cpu_atom@UOPS_RETIRED.FPDIV@) / > tma_info_core_slots", > > + "MetricGroup": "TopdownL3;tma_L3_group;tma_base_group", > > + "MetricName": "tma_other_ret", > > + "MetricThreshold": "tma_other_ret > 0.3", > > + "ScaleUnit": "100%", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Counts the number of machine clears relative to > the number of nuke slots due to page faults.", > > + "MetricExpr": "tma_nuke * > (cpu_atom@MACHINE_CLEARS.PAGE_FAULT@ / > cpu_atom@MACHINE_CLEARS.SLOW@)", > > + "MetricGroup": "TopdownL4;tma_L4_group;tma_nuke_group", > > + "MetricName": "tma_page_fault", > > + "MetricThreshold": "tma_page_fault > 0.02", > > + "ScaleUnit": "100%", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Counts the number of issue slots that were not > delivered by the frontend due to wrong predecodes.", > > + "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.PREDECODE@ / > tma_info_core_slots", > > + "MetricGroup": > "TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", > > + "MetricName": "tma_predecode", > > + "MetricThreshold": "tma_predecode > 0.05", > > + "ScaleUnit": "100%", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Counts the number of issue slots that were not > consumed by the backend due to the physical register file unable to accept an > entry (marble stalls).", > > + "MetricExpr": "cpu_atom@TOPDOWN_BE_BOUND.REGISTER@ / > tma_info_core_slots", > > + "MetricGroup": > "TopdownL3;tma_L3_group;tma_resource_bound_group", > > + "MetricName": "tma_register", > > + "MetricThreshold": "tma_register > 0.1", > > + "ScaleUnit": "100%", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Counts the number of issue slots that were not > consumed by the backend due to the reorder buffer being full (ROB stalls).", > > + "MetricExpr": > "cpu_atom@TOPDOWN_BE_BOUND.REORDER_BUFFER@ / > tma_info_core_slots", > > + "MetricGroup": > "TopdownL3;tma_L3_group;tma_resource_bound_group", > > + "MetricName": "tma_reorder_buffer", > > + "MetricThreshold": "tma_reorder_buffer > 0.1", > > + "ScaleUnit": "100%", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Counts the total number of issue slots that were > not consumed by the backend due to backend stalls", > > + "MetricExpr": "tma_backend_bound", > > + "MetricGroup": > "TopdownL2;tma_L2_group;tma_backend_bound_aux_group", > > + "MetricName": "tma_resource_bound", > > + "MetricThreshold": "tma_resource_bound > 0.2", > > + "MetricgroupNoGroup": "TopdownL2", > > + "PublicDescription": "Counts the total number of issue slots that were > not consumed by the backend due to backend stalls. Note that uops must be > available for consumption in order for this event to count. If a uop is not > available (IQ is empty), this event will not count.", > > + "ScaleUnit": "100%", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Counts the number of issue slots that result in > retirement slots.", > > + "MetricExpr": "cpu_atom@TOPDOWN_RETIRING.ALL@ / > tma_info_core_slots", > > + "MetricGroup": "TopdownL1;tma_L1_group", > > + "MetricName": "tma_retiring", > > + "MetricThreshold": "tma_retiring > 0.75", > > + "MetricgroupNoGroup": "TopdownL1", > > + "ScaleUnit": "100%", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Counts the number of cycles, relative to the > number of mem_scheduler slots, in which uops are blocked due to RSV full > relative", > > + "MetricExpr": "tma_mem_scheduler * > cpu_atom@MEM_SCHEDULER_BLOCK.RSV@ / > MEM_SCHEDULER_BLOCK.ALL", > > + "MetricGroup": > "TopdownL4;tma_L4_group;tma_mem_scheduler_group", > > + "MetricName": "tma_rsv", > > + "MetricThreshold": "tma_rsv > 0.05", > > + "ScaleUnit": "100%", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Counts the number of issue slots that were not > consumed by the backend due to scoreboards from the instruction queue > (IQ), jump execution unit (JEU), or microcode sequencer (MS).", > > + "MetricExpr": "cpu_atom@TOPDOWN_BE_BOUND.SERIALIZATION@ / > tma_info_core_slots", > > + "MetricGroup": > "TopdownL3;tma_L3_group;tma_resource_bound_group", > > + "MetricName": "tma_serialization", > > + "MetricThreshold": "tma_serialization > 0.1", > > + "ScaleUnit": "100%", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Counts the number of machine clears relative to > the number of nuke slots due to SMC.", > > + "MetricExpr": "tma_nuke * (cpu_atom@MACHINE_CLEARS.SMC@ / > cpu_atom@MACHINE_CLEARS.SLOW@)", > > + "MetricGroup": "TopdownL4;tma_L4_group;tma_nuke_group", > > + "MetricName": "tma_smc", > > + "MetricThreshold": "tma_smc > 0.02", > > + "ScaleUnit": "100%", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Counts the number of cycles, relative to the > number of mem_scheduler slots, in which uops are blocked due to store buffer > full", > > + "MetricExpr": "tma_store_bound", > > + "MetricGroup": > "TopdownL4;tma_L4_group;tma_mem_scheduler_group", > > + "MetricName": "tma_st_buffer", > > + "MetricThreshold": "tma_st_buffer > 0.05", > > + "ScaleUnit": "100%", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Counts the number of cycles that the oldest load of > the load buffer is stalled at retirement due to a first level TLB miss.", > > + "MetricExpr": "cpu_atom@LD_HEAD.DTLB_MISS_AT_RET@ / > tma_info_core_clks", > > + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", > > + "MetricName": "tma_stlb_hit", > > + "MetricThreshold": "tma_stlb_hit > 0.05", > > + "ScaleUnit": "100%", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Counts the number of cycles that the oldest load of > the load buffer is stalled at retirement due to a second level TLB miss requiring > a page walk.", > > + "MetricExpr": "cpu_atom@LD_HEAD.PGWALK_AT_RET@ / > tma_info_core_clks", > > + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", > > + "MetricName": "tma_stlb_miss", > > + "MetricThreshold": "tma_stlb_miss > 0.05", > > + "ScaleUnit": "100%", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Counts the number of cycles the core is stalled due > to store buffer full.", > > + "MetricExpr": "tma_mem_scheduler * > (cpu_atom@MEM_SCHEDULER_BLOCK.ST_BUF@ / > cpu_atom@MEM_SCHEDULER_BLOCK.ALL@)", > > + "MetricGroup": > "TopdownL3;tma_L3_group;tma_memory_bound_group", > > + "MetricName": "tma_store_bound", > > + "MetricThreshold": "tma_store_bound > 0.1", > > + "ScaleUnit": "100%", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Counts the number of cycles that the oldest load of > the load buffer is stalled at retirement due to a store forward block.", > > + "MetricExpr": "cpu_atom@LD_HEAD.ST_ADDR_AT_RET@ / > tma_info_core_clks", > > + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", > > + "MetricName": "tma_store_fwd_blk", > > + "MetricThreshold": "tma_store_fwd_blk > 0.05", > > + "ScaleUnit": "100%", > > + "Unit": "cpu_atom" > > + }, > > + { > > + "BriefDescription": "Uncore frequency per die [GHZ]", > > + "MetricExpr": "tma_info_system_socket_clks / #num_dies / > duration_time / 1e9", > > + "MetricGroup": "SoC", > > + "MetricName": "UNCORE_FREQ", > > + "Unit": "cpu_core" > > + }, > > + { > > + "BriefDescription": "This metric represents Core fraction of cycles CPU > dispatched uops on execution ports for ALU operations.", > > + "MetricExpr": "(cpu_core@UOPS_DISPATCHED.PORT_0@ + > cpu_core@UOPS_DISPATCHED.PORT_1@ + > cpu_core@UOPS_DISPATCHED.PORT_5_11@ + > cpu_core@UOPS_DISPATCHED.PORT_6@) / (5 * tma_info_core_core_clks)", > > + "MetricGroup": > "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", > > + "MetricName": "tma_alu_op_utilization", > > + "MetricThreshold": "tma_alu_op_utilization > 0.4", > > + "ScaleUnit": "100%", > > + "Unit": "cpu_core" > > + }, > > + { > > + "BriefDescription": "This metric estimates fraction of slots the CPU > retired uops delivered by the Microcode_Sequencer as a result of Assists", > > + "MetricExpr": "78 * cpu_core@ASSISTS.ANY@ / > tma_info_thread_slots", > > + "MetricGroup": > "TopdownL4;tma_L4_group;tma_microcode_sequencer_group", > > + "MetricName": "tma_assists", > > + "MetricThreshold": "tma_assists > 0.1 & (tma_microcode_sequencer > > 0.05 & tma_heavy_operations > 0.1)", > > + "PublicDescription": "This metric estimates fraction of slots the CPU > retired uops delivered by the Microcode_Sequencer as a result of Assists. > Assists are long sequences of uops that are required in certain corner-cases for > operations that cannot be handled natively by the execution pipeline. For > example; when working with very small floating point values (so-called > Denormals); the FP units are not set up to perform these operations natively. > Instead; a sequence of instructions to perform the computation on the > Denormals is injected into the pipeline. Since these microcode sequences > might be dozens of uops long; Assists can be extremely deleterious to > performance and they can be avoided in many cases. Sample with: > ASSISTS.ANY", > > + "ScaleUnit": "100%", > > + "Unit": "cpu_core" > > + }, > > + { > > + "BriefDescription": "This metric estimates fraction of slots the CPU > retired uops as a result of handing SSE to AVX* or AVX* to SSE transition > Assists.", > > + "MetricExpr": "63 * cpu_core@ASSISTS.SSE_AVX_MIX@ / > tma_info_thread_slots", > > + "MetricGroup": "HPC;TopdownL5;tma_L5_group;tma_assists_group", > > + "MetricName": "tma_avx_assists", > > + "MetricThreshold": "tma_avx_assists > 0.1", > > + "ScaleUnit": "100%", > > + "Unit": "cpu_core" > > + }, > > + { > > + "BriefDescription": "This category represents fraction of slots where no > uops are being delivered due to a lack of required resources for accepting new > uops in the Backend", > > + "MetricExpr": "cpu_core@topdown\\-be\\-bound@ / > (cpu_core@topdown\\-fe\\-bound@ + cpu_core@topdown\\-bad\\-spec@ > + cpu_core@topdown\\-retiring@ + cpu_core@topdown\\-be\\-bound@) + > 0 * tma_info_thread_slots", > > + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", > > + "MetricName": "tma_backend_bound", > > + "MetricThreshold": "tma_backend_bound > 0.2", > > + "MetricgroupNoGroup": "TopdownL1", > > + "PublicDescription": "This category represents fraction of slots where > no uops are being delivered due to a lack of required resources for accepting > new uops in the Backend. Backend is the portion of the processor core where > the out-of-order scheduler dispatches ready uops into their respective > execution units; and once completed these uops get retired according to > program order. For example; stalls due to data-cache misses or stalls due to > the divider unit being overloaded are both categorized under Backend Bound. > Backend Bound is further divided into two main categories: Memory Bound > and Core Bound. Sample with: TOPDOWN.BACKEND_BOUND_SLOTS", > > + "ScaleUnit": "100%", > > + "Unit": "cpu_core" > > + }, > > + { > > + "BriefDescription": "This category represents fraction of slots wasted > due to incorrect speculations", > > + "MetricExpr": "max(1 - (tma_frontend_bound + tma_backend_bound + > tma_retiring), 0)", > > + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", > > + "MetricName": "tma_bad_speculation", > > + "MetricThreshold": "tma_bad_speculation > 0.15", > > + "MetricgroupNoGroup": "TopdownL1", > > + "PublicDescription": "This category represents fraction of slots wasted > due to incorrect speculations. This include slots used to issue uops that do not > eventually get retired and slots for which the issue-pipeline was blocked due to > recovery from earlier incorrect speculation. For example; wasted work due to > miss-predicted branches are categorized under Bad Speculation category. > Incorrect data speculation followed by Memory Ordering Nukes is another > example.", > > + "ScaleUnit": "100%", > > + "Unit": "cpu_core" > > + }, > > + { > > + "BriefDescription": "This metric represents fraction of slots the CPU has > wasted due to Branch Misprediction", > > + "MetricExpr": "cpu_core@topdown\\-br\\-mispredict@ / > (cpu_core@topdown\\-fe\\-bound@ + cpu_core@topdown\\-bad\\-spec@ > + cpu_core@topdown\\-retiring@ + cpu_core@topdown\\-be\\-bound@) + > 0 * tma_info_thread_slots", > > + "MetricGroup": > "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group;tma_bad_specula > tion_group;tma_issueBM", > > + "MetricName": "tma_branch_mispredicts", > > + "MetricThreshold": "tma_branch_mispredicts > 0.1 & > tma_bad_speculation > 0.15", > > + "MetricgroupNoGroup": "TopdownL2", > > + "PublicDescription": "This metric represents fraction of slots the CPU > has wasted due to Branch Misprediction. These slots are either wasted by > uops fetched from an incorrectly speculated program path; or stalls when the > out-of-order part of the machine needs to recover its state from a speculative > path. Sample with: TOPDOWN.BR_MISPREDICT_SLOTS. Related metrics: > tma_info_bad_spec_branch_misprediction_cost, > tma_info_bottleneck_mispredictions, tma_mispredicts_resteers", > > + "ScaleUnit": "100%", > > + "Unit": "cpu_core" > > + }, > > + { > > + "BriefDescription": "This metric represents fraction of cycles the CPU > was stalled due to Branch Resteers", > > + "MetricExpr": "cpu_core@INT_MISC.CLEAR_RESTEER_CYCLES@ / > tma_info_thread_clks + tma_unknown_branches", > > + "MetricGroup": > "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group", > > + "MetricName": "tma_branch_resteers", > > + "MetricThreshold": "tma_branch_resteers > 0.05 & > (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", > > + "PublicDescription": "This metric represents fraction of cycles the CPU > was stalled due to Branch Resteers. Branch Resteers estimates the Frontend > delay in fetching operations from corrected path; following all sorts of miss- > predicted branches. For example; branchy code with lots of miss-predictions > might get categorized under Branch Resteers. Note the value of this node may > overlap with its siblings. Sample with: BR_MISP_RETIRED.ALL_BRANCHES", > > + "ScaleUnit": "100%", > > + "Unit": "cpu_core" > > + }, > > + { > > + "BriefDescription": "This metric represents fraction of cycles the CPU > was stalled due staying in C0.1 power-performance optimized state (Faster > wakeup time; Smaller power savings).", > > + "MetricExpr": "cpu_core@CPU_CLK_UNHALTED.C01@ / > tma_info_thread_clks", > > + "MetricGroup": > "C0Wait;TopdownL4;tma_L4_group;tma_serializing_operation_group", > > + "MetricName": "tma_c01_wait", > > + "MetricThreshold": "tma_c01_wait > 0.05 & > (tma_serializing_operation > 0.1 & (tma_core_bound > 0.1 & > tma_backend_bound > 0.2))", > > + "ScaleUnit": "100%", > > + "Unit": "cpu_core" > > + }, > > + { > > + "BriefDescription": "This metric represents fraction of cycles the CPU > was stalled due staying in C0.2 power-performance optimized state (Slower > wakeup time; Larger power savings).", > > + "MetricExpr": "cpu_core@CPU_CLK_UNHALTED.C02@ / > tma_info_thread_clks", > > + "MetricGroup": > "C0Wait;TopdownL4;tma_L4_group;tma_serializing_operation_group", > > + "MetricName": "tma_c02_wait", > > + "MetricThreshold": "tma_c02_wait > 0.05 & > (tma_serializing_operation > 0.1 & (tma_core_bound > 0.1 & > tma_backend_bound > 0.2))", > > + "ScaleUnit": "100%", > > + "Unit": "cpu_core" > > + }, > > + { > > + "BriefDescription": "This metric estimates fraction of cycles the CPU > retired uops originated from CISC (complex instruction set computer) > instruction", > > + "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)", > > + "MetricGroup": > "TopdownL4;tma_L4_group;tma_microcode_sequencer_group", > > + "MetricName": "tma_cisc", > > + "MetricThreshold": "tma_cisc > 0.1 & (tma_microcode_sequencer > > 0.05 & tma_heavy_operations > 0.1)", > > + "PublicDescription": "This metric estimates fraction of cycles the CPU > retired uops originated from CISC (complex instruction set computer) > instruction. A CISC instruction has multiple uops that are required to perform > the instruction's functionality as in the case of read-modify-write as an > example. Since these instructions require multiple uops they may or may not > imply sub-optimal use of machine resources. Sample with: > FRONTEND_RETIRED.MS_FLOWS", > > + "ScaleUnit": "100%", > > + "Unit": "cpu_core" > > + }, > > + { > > + "BriefDescription": "This metric represents fraction of cycles the CPU > was stalled due to Branch Resteers as a result of Machine Clears", > > + "MetricExpr": "(1 - tma_branch_mispredicts / tma_bad_speculation) * > cpu_core@INT_MISC.CLEAR_RESTEER_CYCLES@ / tma_info_thread_clks", > > + "MetricGroup": > "BadSpec;MachineClears;TopdownL4;tma_L4_group;tma_branch_resteers_gr > oup;tma_issueMC", > > + "MetricName": "tma_clears_resteers", > > + "MetricThreshold": "tma_clears_resteers > 0.05 & > (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & > tma_frontend_bound > 0.15))", > > + "PublicDescription": "This metric represents fraction of cycles the CPU > was stalled due to Branch Resteers as a result of Machine Clears. Sample with: > INT_MISC.CLEAR_RESTEER_CYCLES. Related metrics: tma_l1_bound, > tma_machine_clears, tma_microcode_sequencer, tma_ms_switches", > > + "ScaleUnit": "100%", > > + "Unit": "cpu_core" > > + }, > > + { > > + "BriefDescription": "This metric estimates fraction of cycles while the > memory subsystem was handling synchronizations due to contested > accesses", > > + "MetricExpr": > "(cpu_core@MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS@ * > min(cpu_core@MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS@:retire_latency, > 24 * tma_info_system_core_frequency) + > cpu_core@MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD@ * > min(cpu_core@MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD@:retire_latency, 25 > * tma_info_system_core_frequency) * > (cpu_core@OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM@ / > (cpu_core@OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM@ + > cpu_core@OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD@))) * (1 > + cpu_core@MEM_LOAD_RETIRED.FB_HIT@ / > cpu_core@MEM_LOAD_RETIRED.L1_MISS@ / 2) / tma_info_thread_clks", > > Thanks Weilin! The modifier on an event doesn't usually have the colon > when there is a slash. So: > cpu_core@MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD@:retire_latency > Should be: > cpu_core@MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD@retire_latency Thanks Ian! I will update this accordingly. > The modifiers also tend to be a single character. The modifier 'R' is > unused, so I wonder we can use it here so that we can support these > events not just in metrics. Do you mean we use 'R' instead of "retire_latency" in all the formulas? I could do this Update. > > Ian ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [RFC PATCH v2 6/6] perf vendor events intel: Add MTL metric json files 2024-02-29 1:36 ` Wang, Weilin @ 2024-02-29 2:01 ` Ian Rogers 0 siblings, 0 replies; 10+ messages in thread From: Ian Rogers @ 2024-02-29 2:01 UTC (permalink / raw) To: Wang, Weilin Cc: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo, Alexander Shishkin, Jiri Olsa, Namhyung Kim, Hunter, Adrian, Kan Liang, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Taylor, Perry, Alt, Samantha, Biggers, Caleb On Wed, Feb 28, 2024 at 5:36 PM Wang, Weilin <weilin.wang@intel.com> wrote: > > > > > -----Original Message----- > > From: Ian Rogers <irogers@google.com> > > Sent: Wednesday, February 28, 2024 8:50 AM > > To: Wang, Weilin <weilin.wang@intel.com> > > Cc: Peter Zijlstra <peterz@infradead.org>; Ingo Molnar <mingo@redhat.com>; > > Arnaldo Carvalho de Melo <acme@kernel.org>; Alexander Shishkin > > <alexander.shishkin@linux.intel.com>; Jiri Olsa <jolsa@kernel.org>; Namhyung > > Kim <namhyung@kernel.org>; Hunter, Adrian <adrian.hunter@intel.com>; > > Kan Liang <kan.liang@linux.intel.com>; linux-perf-users@vger.kernel.org; > > linux-kernel@vger.kernel.org; Taylor, Perry <perry.taylor@intel.com>; Alt, > > Samantha <samantha.alt@intel.com>; Biggers, Caleb > > <caleb.biggers@intel.com> > > Subject: Re: [RFC PATCH v2 6/6] perf vendor events intel: Add MTL metric json > > files > > > > On Wed, Feb 28, 2024 at 8:12 AM <weilin.wang@intel.com> wrote: > > > > > > From: Weilin Wang <weilin.wang@intel.com> > > > > > > Add MTL metric json file at TMA4.7 [1]. Some of the metrics' formulas use > > TPEBS > > > retire_latency in MTL. > > > > > > [1] https://lore.kernel.org/all/20240214011820.644458-1- > > irogers@google.com/ > > > > > > Signed-off-by: Weilin Wang <weilin.wang@intel.com> > > > --- > > > .../arch/x86/meteorlake/metricgroups.json | 127 + > > > .../arch/x86/meteorlake/mtl-metrics.json | 2531 +++++++++++++++++ > > > 2 files changed, 2658 insertions(+) > > > create mode 100644 tools/perf/pmu- > > events/arch/x86/meteorlake/metricgroups.json > > > create mode 100644 tools/perf/pmu-events/arch/x86/meteorlake/mtl- > > metrics.json > > > > > > diff --git a/tools/perf/pmu-events/arch/x86/meteorlake/metricgroups.json > > b/tools/perf/pmu-events/arch/x86/meteorlake/metricgroups.json > > > new file mode 100644 > > > index 000000000000..7a03835f262c > > > --- /dev/null > > > +++ b/tools/perf/pmu-events/arch/x86/meteorlake/metricgroups.json > > > @@ -0,0 +1,127 @@ > > > +{ > > > + "Backend": "Grouping from Top-down Microarchitecture Analysis Metrics > > spreadsheet", > > > + "Bad": "Grouping from Top-down Microarchitecture Analysis Metrics > > spreadsheet", > > > + "BadSpec": "Grouping from Top-down Microarchitecture Analysis Metrics > > spreadsheet", > > > + "BigFootprint": "Grouping from Top-down Microarchitecture Analysis > > Metrics spreadsheet", > > > + "BrMispredicts": "Grouping from Top-down Microarchitecture Analysis > > Metrics spreadsheet", > > > + "Branches": "Grouping from Top-down Microarchitecture Analysis > > Metrics spreadsheet", > > > + "C0Wait": "Grouping from Top-down Microarchitecture Analysis Metrics > > spreadsheet", > > > + "CacheHits": "Grouping from Top-down Microarchitecture Analysis > > Metrics spreadsheet", > > > + "CodeGen": "Grouping from Top-down Microarchitecture Analysis > > Metrics spreadsheet", > > > + "Compute": "Grouping from Top-down Microarchitecture Analysis > > Metrics spreadsheet", > > > + "Cor": "Grouping from Top-down Microarchitecture Analysis Metrics > > spreadsheet", > > > + "DSB": "Grouping from Top-down Microarchitecture Analysis Metrics > > spreadsheet", > > > + "DSBmiss": "Grouping from Top-down Microarchitecture Analysis Metrics > > spreadsheet", > > > + "DataSharing": "Grouping from Top-down Microarchitecture Analysis > > Metrics spreadsheet", > > > + "Fed": "Grouping from Top-down Microarchitecture Analysis Metrics > > spreadsheet", > > > + "FetchBW": "Grouping from Top-down Microarchitecture Analysis > > Metrics spreadsheet", > > > + "FetchLat": "Grouping from Top-down Microarchitecture Analysis Metrics > > spreadsheet", > > > + "Flops": "Grouping from Top-down Microarchitecture Analysis Metrics > > spreadsheet", > > > + "FpScalar": "Grouping from Top-down Microarchitecture Analysis Metrics > > spreadsheet", > > > + "FpVector": "Grouping from Top-down Microarchitecture Analysis > > Metrics spreadsheet", > > > + "Frontend": "Grouping from Top-down Microarchitecture Analysis > > Metrics spreadsheet", > > > + "HPC": "Grouping from Top-down Microarchitecture Analysis Metrics > > spreadsheet", > > > + "IcMiss": "Grouping from Top-down Microarchitecture Analysis Metrics > > spreadsheet", > > > + "InsType": "Grouping from Top-down Microarchitecture Analysis Metrics > > spreadsheet", > > > + "IntVector": "Grouping from Top-down Microarchitecture Analysis > > Metrics spreadsheet", > > > + "L2Evicts": "Grouping from Top-down Microarchitecture Analysis Metrics > > spreadsheet", > > > + "LSD": "Grouping from Top-down Microarchitecture Analysis Metrics > > spreadsheet", > > > + "MachineClears": "Grouping from Top-down Microarchitecture Analysis > > Metrics spreadsheet", > > > + "Machine_Clears": "Grouping from Top-down Microarchitecture Analysis > > Metrics spreadsheet", > > > + "Mem": "Grouping from Top-down Microarchitecture Analysis Metrics > > spreadsheet", > > > + "MemOffcore": "Grouping from Top-down Microarchitecture Analysis > > Metrics spreadsheet", > > > + "MemoryBW": "Grouping from Top-down Microarchitecture Analysis > > Metrics spreadsheet", > > > + "MemoryBound": "Grouping from Top-down Microarchitecture Analysis > > Metrics spreadsheet", > > > + "MemoryLat": "Grouping from Top-down Microarchitecture Analysis > > Metrics spreadsheet", > > > + "MemoryTLB": "Grouping from Top-down Microarchitecture Analysis > > Metrics spreadsheet", > > > + "Memory_BW": "Grouping from Top-down Microarchitecture Analysis > > Metrics spreadsheet", > > > + "Memory_Lat": "Grouping from Top-down Microarchitecture Analysis > > Metrics spreadsheet", > > > + "MicroSeq": "Grouping from Top-down Microarchitecture Analysis > > Metrics spreadsheet", > > > + "OS": "Grouping from Top-down Microarchitecture Analysis Metrics > > spreadsheet", > > > + "Offcore": "Grouping from Top-down Microarchitecture Analysis Metrics > > spreadsheet", > > > + "PGO": "Grouping from Top-down Microarchitecture Analysis Metrics > > spreadsheet", > > > + "Pipeline": "Grouping from Top-down Microarchitecture Analysis Metrics > > spreadsheet", > > > + "PortsUtil": "Grouping from Top-down Microarchitecture Analysis Metrics > > spreadsheet", > > > + "Power": "Grouping from Top-down Microarchitecture Analysis Metrics > > spreadsheet", > > > + "Prefetches": "Grouping from Top-down Microarchitecture Analysis > > Metrics spreadsheet", > > > + "Ret": "Grouping from Top-down Microarchitecture Analysis Metrics > > spreadsheet", > > > + "Retire": "Grouping from Top-down Microarchitecture Analysis Metrics > > spreadsheet", > > > + "SMT": "Grouping from Top-down Microarchitecture Analysis Metrics > > spreadsheet", > > > + "Server": "Grouping from Top-down Microarchitecture Analysis Metrics > > spreadsheet", > > > + "Snoop": "Grouping from Top-down Microarchitecture Analysis Metrics > > spreadsheet", > > > + "SoC": "Grouping from Top-down Microarchitecture Analysis Metrics > > spreadsheet", > > > + "Summary": "Grouping from Top-down Microarchitecture Analysis > > Metrics spreadsheet", > > > + "TmaL1": "Grouping from Top-down Microarchitecture Analysis Metrics > > spreadsheet", > > > + "TmaL2": "Grouping from Top-down Microarchitecture Analysis Metrics > > spreadsheet", > > > + "TmaL3mem": "Grouping from Top-down Microarchitecture Analysis > > Metrics spreadsheet", > > > + "TopdownL1": "Metrics for top-down breakdown at level 1", > > > + "TopdownL2": "Metrics for top-down breakdown at level 2", > > > + "TopdownL3": "Metrics for top-down breakdown at level 3", > > > + "TopdownL4": "Metrics for top-down breakdown at level 4", > > > + "TopdownL5": "Metrics for top-down breakdown at level 5", > > > + "TopdownL6": "Metrics for top-down breakdown at level 6", > > > + "tma_L1_group": "Metrics for top-down breakdown at level 1", > > > + "tma_L2_group": "Metrics for top-down breakdown at level 2", > > > + "tma_L3_group": "Metrics for top-down breakdown at level 3", > > > + "tma_L4_group": "Metrics for top-down breakdown at level 4", > > > + "tma_L5_group": "Metrics for top-down breakdown at level 5", > > > + "tma_L6_group": "Metrics for top-down breakdown at level 6", > > > + "tma_alu_op_utilization_group": "Metrics contributing to > > tma_alu_op_utilization category", > > > + "tma_assists_group": "Metrics contributing to tma_assists category", > > > + "tma_backend_bound_aux_group": "Metrics contributing to > > tma_backend_bound_aux category", > > > + "tma_backend_bound_group": "Metrics contributing to > > tma_backend_bound category", > > > + "tma_bad_speculation_group": "Metrics contributing to > > tma_bad_speculation category", > > > + "tma_base_group": "Metrics contributing to tma_base category", > > > + "tma_branch_mispredicts_group": "Metrics contributing to > > tma_branch_mispredicts category", > > > + "tma_branch_resteers_group": "Metrics contributing to > > tma_branch_resteers category", > > > + "tma_core_bound_group": "Metrics contributing to tma_core_bound > > category", > > > + "tma_dram_bound_group": "Metrics contributing to tma_dram_bound > > category", > > > + "tma_dtlb_load_group": "Metrics contributing to tma_dtlb_load > > category", > > > + "tma_dtlb_store_group": "Metrics contributing to tma_dtlb_store > > category", > > > + "tma_fetch_bandwidth_group": "Metrics contributing to > > tma_fetch_bandwidth category", > > > + "tma_fetch_latency_group": "Metrics contributing to tma_fetch_latency > > category", > > > + "tma_fp_arith_group": "Metrics contributing to tma_fp_arith category", > > > + "tma_fp_vector_group": "Metrics contributing to tma_fp_vector > > category", > > > + "tma_frontend_bound_group": "Metrics contributing to > > tma_frontend_bound category", > > > + "tma_heavy_operations_group": "Metrics contributing to > > tma_heavy_operations category", > > > + "tma_int_operations_group": "Metrics contributing to > > tma_int_operations category", > > > + "tma_issue2P": "Metrics related by the issue $issue2P", > > > + "tma_issueBM": "Metrics related by the issue $issueBM", > > > + "tma_issueBW": "Metrics related by the issue $issueBW", > > > + "tma_issueComp": "Metrics related by the issue $issueComp", > > > + "tma_issueD0": "Metrics related by the issue $issueD0", > > > + "tma_issueFB": "Metrics related by the issue $issueFB", > > > + "tma_issueFL": "Metrics related by the issue $issueFL", > > > + "tma_issueL1": "Metrics related by the issue $issueL1", > > > + "tma_issueLat": "Metrics related by the issue $issueLat", > > > + "tma_issueMC": "Metrics related by the issue $issueMC", > > > + "tma_issueMS": "Metrics related by the issue $issueMS", > > > + "tma_issueMV": "Metrics related by the issue $issueMV", > > > + "tma_issueRFO": "Metrics related by the issue $issueRFO", > > > + "tma_issueSL": "Metrics related by the issue $issueSL", > > > + "tma_issueSO": "Metrics related by the issue $issueSO", > > > + "tma_issueSmSt": "Metrics related by the issue $issueSmSt", > > > + "tma_issueSpSt": "Metrics related by the issue $issueSpSt", > > > + "tma_issueSyncxn": "Metrics related by the issue $issueSyncxn", > > > + "tma_issueTLB": "Metrics related by the issue $issueTLB", > > > + "tma_l1_bound_group": "Metrics contributing to tma_l1_bound > > category", > > > + "tma_l3_bound_group": "Metrics contributing to tma_l3_bound > > category", > > > + "tma_light_operations_group": "Metrics contributing to > > tma_light_operations category", > > > + "tma_load_op_utilization_group": "Metrics contributing to > > tma_load_op_utilization category", > > > + "tma_machine_clears_group": "Metrics contributing to > > tma_machine_clears category", > > > + "tma_mem_latency_group": "Metrics contributing to tma_mem_latency > > category", > > > + "tma_mem_scheduler_group": "Metrics contributing to > > tma_mem_scheduler category", > > > + "tma_memory_bound_group": "Metrics contributing to > > tma_memory_bound category", > > > + "tma_microcode_sequencer_group": "Metrics contributing to > > tma_microcode_sequencer category", > > > + "tma_mite_group": "Metrics contributing to tma_mite category", > > > + "tma_nuke_group": "Metrics contributing to tma_nuke category", > > > + "tma_other_light_ops_group": "Metrics contributing to > > tma_other_light_ops category", > > > + "tma_ports_utilization_group": "Metrics contributing to > > tma_ports_utilization category", > > > + "tma_ports_utilized_0_group": "Metrics contributing to > > tma_ports_utilized_0 category", > > > + "tma_ports_utilized_3m_group": "Metrics contributing to > > tma_ports_utilized_3m category", > > > + "tma_resource_bound_group": "Metrics contributing to > > tma_resource_bound category", > > > + "tma_retiring_group": "Metrics contributing to tma_retiring category", > > > + "tma_serializing_operation_group": "Metrics contributing to > > tma_serializing_operation category", > > > + "tma_store_bound_group": "Metrics contributing to tma_store_bound > > category", > > > + "tma_store_op_utilization_group": "Metrics contributing to > > tma_store_op_utilization category" > > > +} > > > diff --git a/tools/perf/pmu-events/arch/x86/meteorlake/mtl-metrics.json > > b/tools/perf/pmu-events/arch/x86/meteorlake/mtl-metrics.json > > > new file mode 100644 > > > index 000000000000..12df19538fd6 > > > --- /dev/null > > > +++ b/tools/perf/pmu-events/arch/x86/meteorlake/mtl-metrics.json > > > @@ -0,0 +1,2531 @@ > > > +[ > > > + { > > > + "BriefDescription": "C10 residency percent per package", > > > + "MetricExpr": "cstate_pkg@c10\\-residency@ / TSC", > > > + "MetricGroup": "Power", > > > + "MetricName": "C10_Pkg_Residency", > > > + "ScaleUnit": "100%" > > > + }, > > > + { > > > + "BriefDescription": "C1 residency percent per core", > > > + "MetricExpr": "cstate_core@c1\\-residency@ / TSC", > > > + "MetricGroup": "Power", > > > + "MetricName": "C1_Core_Residency", > > > + "ScaleUnit": "100%" > > > + }, > > > + { > > > + "BriefDescription": "C2 residency percent per package", > > > + "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC", > > > + "MetricGroup": "Power", > > > + "MetricName": "C2_Pkg_Residency", > > > + "ScaleUnit": "100%" > > > + }, > > > + { > > > + "BriefDescription": "C3 residency percent per package", > > > + "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC", > > > + "MetricGroup": "Power", > > > + "MetricName": "C3_Pkg_Residency", > > > + "ScaleUnit": "100%" > > > + }, > > > + { > > > + "BriefDescription": "C6 residency percent per core", > > > + "MetricExpr": "cstate_core@c6\\-residency@ / TSC", > > > + "MetricGroup": "Power", > > > + "MetricName": "C6_Core_Residency", > > > + "ScaleUnit": "100%" > > > + }, > > > + { > > > + "BriefDescription": "C6 residency percent per package", > > > + "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC", > > > + "MetricGroup": "Power", > > > + "MetricName": "C6_Pkg_Residency", > > > + "ScaleUnit": "100%" > > > + }, > > > + { > > > + "BriefDescription": "C7 residency percent per core", > > > + "MetricExpr": "cstate_core@c7\\-residency@ / TSC", > > > + "MetricGroup": "Power", > > > + "MetricName": "C7_Core_Residency", > > > + "ScaleUnit": "100%" > > > + }, > > > + { > > > + "BriefDescription": "C7 residency percent per package", > > > + "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC", > > > + "MetricGroup": "Power", > > > + "MetricName": "C7_Pkg_Residency", > > > + "ScaleUnit": "100%" > > > + }, > > > + { > > > + "BriefDescription": "C8 residency percent per package", > > > + "MetricExpr": "cstate_pkg@c8\\-residency@ / TSC", > > > + "MetricGroup": "Power", > > > + "MetricName": "C8_Pkg_Residency", > > > + "ScaleUnit": "100%" > > > + }, > > > + { > > > + "BriefDescription": "C9 residency percent per package", > > > + "MetricExpr": "cstate_pkg@c9\\-residency@ / TSC", > > > + "MetricGroup": "Power", > > > + "MetricName": "C9_Pkg_Residency", > > > + "ScaleUnit": "100%" > > > + }, > > > + { > > > + "BriefDescription": "Percentage of cycles spent in System Management > > Interrupts.", > > > + "MetricExpr": "((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > > > 0 else 0)", > > > + "MetricGroup": "smi", > > > + "MetricName": "smi_cycles", > > > + "MetricThreshold": "smi_cycles > 0.1", > > > + "ScaleUnit": "100%" > > > + }, > > > + { > > > + "BriefDescription": "Number of SMI interrupts.", > > > + "MetricExpr": "msr@smi@", > > > + "MetricGroup": "smi", > > > + "MetricName": "smi_num", > > > + "ScaleUnit": "1SMI#" > > > + }, > > > + { > > > + "BriefDescription": "Counts the number of issue slots that were not > > consumed by the backend due to certain allocation restrictions.", > > > + "MetricExpr": > > "cpu_atom@TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS@ / > > tma_info_core_slots", > > > + "MetricGroup": > > "TopdownL3;tma_L3_group;tma_resource_bound_group", > > > + "MetricName": "tma_alloc_restriction", > > > + "MetricThreshold": "tma_alloc_restriction > 0.1", > > > + "ScaleUnit": "100%", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Counts the total number of issue slots that were > > not consumed by the backend due to backend stalls", > > > + "MetricExpr": "cpu_atom@TOPDOWN_BE_BOUND.ALL@ / > > tma_info_core_slots", > > > + "MetricGroup": "TopdownL1;tma_L1_group", > > > + "MetricName": "tma_backend_bound", > > > + "MetricThreshold": "tma_backend_bound > 0.1", > > > + "MetricgroupNoGroup": "TopdownL1", > > > + "PublicDescription": "Counts the total number of issue slots that were > > not consumed by the backend due to backend stalls. Note that uops must be > > available for consumption in order for this event to count. If a uop is not > > available (IQ is empty), this event will not count. The rest of these subevents > > count backend stalls, in cycles, due to an outstanding request which is > > memory bound vs core bound. The subevents are not slot based events and > > therefore can not be precisely added or subtracted from the > > Backend_Bound_Aux subevents which are slot based.", > > > + "ScaleUnit": "100%", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Counts the total number of issue slots that were > > not consumed by the backend due to backend stalls", > > > + "MetricExpr": "tma_backend_bound", > > > + "MetricGroup": "TopdownL1;tma_L1_group", > > > + "MetricName": "tma_backend_bound_aux", > > > + "MetricThreshold": "tma_backend_bound_aux > 0.2", > > > + "MetricgroupNoGroup": "TopdownL1", > > > + "PublicDescription": "Counts the total number of issue slots that were > > not consumed by the backend due to backend stalls. Note that UOPS must be > > available for consumption in order for this event to count. If a uop is not > > available (IQ is empty), this event will not count. All of these subevents count > > backend stalls, in slots, due to a resource limitation. These are not cycle based > > events and therefore can not be precisely added or subtracted from the > > Backend_Bound subevents which are cycle based. These subevents are > > supplementary to Backend_Bound and can be used to analyze results from a > > resource perspective at allocation.", > > > + "ScaleUnit": "100%", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Counts the total number of issue slots that were > > not consumed by the backend because allocation is stalled due to a > > mispredicted jump or a machine clear", > > > + "MetricExpr": "cpu_atom@TOPDOWN_BAD_SPECULATION.ALL@ / > > tma_info_core_slots", > > > + "MetricGroup": "TopdownL1;tma_L1_group", > > > + "MetricName": "tma_bad_speculation", > > > + "MetricThreshold": "tma_bad_speculation > 0.15", > > > + "MetricgroupNoGroup": "TopdownL1", > > > + "PublicDescription": "Counts the total number of issue slots that were > > not consumed by the backend because allocation is stalled due to a > > mispredicted jump or a machine clear. Only issue slots wasted due to fast > > nukes such as memory ordering nukes are counted. Other nukes are not > > accounted for. Counts all issue slots blocked during this recovery window > > including relevant microcode flows and while uops are not yet available in the > > instruction queue (IQ). Also includes the issue slots that were consumed by > > the backend but were thrown away because they were younger than the > > mispredict or machine clear.", > > > + "ScaleUnit": "100%", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Counts the number of uops that are not from the > > microsequencer.", > > > + "MetricExpr": "(cpu_atom@TOPDOWN_RETIRING.ALL@ - > > cpu_atom@UOPS_RETIRED.MS@) / tma_info_core_slots", > > > + "MetricGroup": "TopdownL2;tma_L2_group;tma_retiring_group", > > > + "MetricName": "tma_base", > > > + "MetricThreshold": "tma_base > 0.6", > > > + "MetricgroupNoGroup": "TopdownL2", > > > + "ScaleUnit": "100%", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Counts the number of issue slots that were not > > delivered by the frontend due to BACLEARS, which occurs when the Branch > > Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch > > predictor in the frontend", > > > + "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.BRANCH_DETECT@ > > / tma_info_core_slots", > > > + "MetricGroup": > > "TopdownL3;tma_L3_group;tma_fetch_latency_group", > > > + "MetricName": "tma_branch_detect", > > > + "MetricThreshold": "tma_branch_detect > 0.05", > > > + "PublicDescription": "Counts the number of issue slots that were not > > delivered by the frontend due to BACLEARS, which occurs when the Branch > > Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch > > predictor in the frontend. Includes BACLEARS due to all branch types including > > conditional and unconditional jumps, returns, and indirect branches.", > > > + "ScaleUnit": "100%", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Counts the number of issue slots that were not > > consumed by the backend due to branch mispredicts.", > > > + "MetricExpr": > > "cpu_atom@TOPDOWN_BAD_SPECULATION.MISPREDICT@ / > > tma_info_core_slots", > > > + "MetricGroup": > > "TopdownL2;tma_L2_group;tma_bad_speculation_group", > > > + "MetricName": "tma_branch_mispredicts", > > > + "MetricThreshold": "tma_branch_mispredicts > 0.05", > > > + "MetricgroupNoGroup": "TopdownL2", > > > + "ScaleUnit": "100%", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Counts the number of issue slots that were not > > delivered by the frontend due to BTCLEARS, which occurs when the Branch > > Target Buffer (BTB) predicts a taken branch.", > > > + "MetricExpr": > > "cpu_atom@TOPDOWN_FE_BOUND.BRANCH_RESTEER@ / > > tma_info_core_slots", > > > + "MetricGroup": > > "TopdownL3;tma_L3_group;tma_fetch_latency_group", > > > + "MetricName": "tma_branch_resteer", > > > + "MetricThreshold": "tma_branch_resteer > 0.05", > > > + "ScaleUnit": "100%", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Counts the number of issue slots that were not > > delivered by the frontend due to the microcode sequencer (MS).", > > > + "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.CISC@ / > > tma_info_core_slots", > > > + "MetricGroup": > > "TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", > > > + "MetricName": "tma_cisc", > > > + "MetricThreshold": "tma_cisc > 0.05", > > > + "ScaleUnit": "100%", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Counts the number of cycles due to backend > > bound stalls that are core execution bound and not attributed to outstanding > > demand load or store stalls.", > > > + "MetricExpr": "max(0, tma_backend_bound - tma_memory_bound)", > > > + "MetricGroup": > > "TopdownL2;tma_L2_group;tma_backend_bound_group", > > > + "MetricName": "tma_core_bound", > > > + "MetricThreshold": "tma_core_bound > 0.1", > > > + "MetricgroupNoGroup": "TopdownL2", > > > + "ScaleUnit": "100%", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Counts the number of issue slots that were not > > delivered by the frontend due to decode stalls.", > > > + "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.DECODE@ / > > tma_info_core_slots", > > > + "MetricGroup": > > "TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", > > > + "MetricName": "tma_decode", > > > + "MetricThreshold": "tma_decode > 0.05", > > > + "ScaleUnit": "100%", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Counts the number of machine clears relative to > > the number of nuke slots due to memory disambiguation.", > > > + "MetricExpr": "tma_nuke * > > (cpu_atom@MACHINE_CLEARS.DISAMBIGUATION@ / > > cpu_atom@MACHINE_CLEARS.SLOW@)", > > > + "MetricGroup": "TopdownL4;tma_L4_group;tma_nuke_group", > > > + "MetricName": "tma_disambiguation", > > > + "MetricThreshold": "tma_disambiguation > 0.02", > > > + "ScaleUnit": "100%", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Counts the number of cycles the core is stalled due > > to a demand load miss which hit in DRAM or MMIO (Non-DRAM).", > > > + "MetricExpr": "cpu_atom@MEM_BOUND_STALLS_LOAD.LLC_MISS@ / > > tma_info_core_clks - max((cpu_atom@MEM_BOUND_STALLS_LOAD.ALL@ - > > cpu_atom@LD_HEAD.L1_MISS_AT_RET@) / tma_info_core_clks, 0) * > > cpu_atom@MEM_BOUND_STALLS_LOAD.LLC_MISS@ / > > cpu_atom@MEM_BOUND_STALLS_LOAD.ALL@", > > > + "MetricGroup": > > "TopdownL3;tma_L3_group;tma_memory_bound_group", > > > + "MetricName": "tma_dram_bound", > > > + "MetricThreshold": "tma_dram_bound > 0.1", > > > + "ScaleUnit": "100%", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Counts the number of issue slots that were not > > consumed by the backend due to a machine clear classified as a fast nuke due > > to memory ordering, memory disambiguation and memory renaming.", > > > + "MetricExpr": > > "cpu_atom@TOPDOWN_BAD_SPECULATION.FASTNUKE@ / > > tma_info_core_slots", > > > + "MetricGroup": > > "TopdownL3;tma_L3_group;tma_machine_clears_group", > > > + "MetricName": "tma_fast_nuke", > > > + "MetricThreshold": "tma_fast_nuke > 0.05", > > > + "ScaleUnit": "100%", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Counts the number of issue slots that were not > > delivered by the frontend due to frontend bandwidth restrictions due to > > decode, predecode, cisc, and other limitations.", > > > + "MetricExpr": > > "cpu_atom@TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH@ / > > tma_info_core_slots", > > > + "MetricGroup": > > "TopdownL2;tma_L2_group;tma_frontend_bound_group", > > > + "MetricName": "tma_fetch_bandwidth", > > > + "MetricThreshold": "tma_fetch_bandwidth > 0.1", > > > + "MetricgroupNoGroup": "TopdownL2", > > > + "ScaleUnit": "100%", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Counts the number of issue slots that were not > > delivered by the frontend due to frontend bandwidth restrictions due to > > decode, predecode, cisc, and other limitations.", > > > + "MetricExpr": > > "cpu_atom@TOPDOWN_FE_BOUND.FRONTEND_LATENCY@ / > > tma_info_core_slots", > > > + "MetricGroup": > > "TopdownL2;tma_L2_group;tma_frontend_bound_group", > > > + "MetricName": "tma_fetch_latency", > > > + "MetricThreshold": "tma_fetch_latency > 0.15", > > > + "MetricgroupNoGroup": "TopdownL2", > > > + "ScaleUnit": "100%", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Counts the number of machine clears relative to > > the number of nuke slots due to FP assists.", > > > + "MetricExpr": "tma_nuke * > > (cpu_atom@MACHINE_CLEARS.FP_ASSIST@ / > > cpu_atom@MACHINE_CLEARS.SLOW@)", > > > + "MetricGroup": "TopdownL4;tma_L4_group;tma_nuke_group", > > > + "MetricName": "tma_fp_assist", > > > + "MetricThreshold": "tma_fp_assist > 0.02", > > > + "ScaleUnit": "100%", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Counts the number of floating point divide > > operations per uop.", > > > + "MetricExpr": "cpu_atom@UOPS_RETIRED.FPDIV@ / > > tma_info_core_slots", > > > + "MetricGroup": "TopdownL3;tma_L3_group;tma_base_group", > > > + "MetricName": "tma_fpdiv_uops", > > > + "MetricThreshold": "tma_fpdiv_uops > 0.2", > > > + "ScaleUnit": "100%", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Counts the number of issue slots that were not > > consumed by the backend due to frontend stalls.", > > > + "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.ALL@ / > > tma_info_core_slots", > > > + "MetricGroup": "TopdownL1;tma_L1_group", > > > + "MetricName": "tma_frontend_bound", > > > + "MetricThreshold": "tma_frontend_bound > 0.2", > > > + "MetricgroupNoGroup": "TopdownL1", > > > + "ScaleUnit": "100%", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Counts the number of issue slots that were not > > delivered by the frontend due to instruction cache misses.", > > > + "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.ICACHE@ / > > tma_info_core_slots", > > > + "MetricGroup": > > "TopdownL3;tma_L3_group;tma_fetch_latency_group", > > > + "MetricName": "tma_icache_misses", > > > + "MetricThreshold": "tma_icache_misses > 0.05", > > > + "ScaleUnit": "100%", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "", > > > + "MetricExpr": "cpu_atom@CPU_CLK_UNHALTED.CORE@", > > > + "MetricName": "tma_info_core_clks", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "", > > > + "MetricExpr": "cpu_atom@CPU_CLK_UNHALTED.CORE_P@", > > > + "MetricName": "tma_info_core_clks_p", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Cycles Per Instruction", > > > + "MetricExpr": "tma_info_core_clks / INST_RETIRED.ANY", > > > + "MetricName": "tma_info_core_cpi", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Instructions Per Cycle", > > > + "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / > > tma_info_core_clks", > > > + "MetricName": "tma_info_core_ipc", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "", > > > + "MetricExpr": "6 * tma_info_core_clks", > > > + "MetricName": "tma_info_core_slots", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Uops Per Instruction", > > > + "MetricExpr": "cpu_atom@UOPS_RETIRED.ALL@ / > > INST_RETIRED.ANY", > > > + "MetricName": "tma_info_core_upi", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Percent of instruction miss cost that hit in DRAM", > > > + "MetricExpr": "100 * > > cpu_atom@MEM_BOUND_STALLS_IFETCH.LLC_MISS@ / > > cpu_atom@MEM_BOUND_STALLS_IFETCH.ALL@", > > > + "MetricName": "tma_info_frontend_inst_miss_cost_dramhit_percent", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Percent of instruction miss cost that hit in the L2", > > > + "MetricExpr": "100 * > > cpu_atom@MEM_BOUND_STALLS_IFETCH.L2_HIT@ / > > cpu_atom@MEM_BOUND_STALLS_IFETCH.ALL@", > > > + "MetricName": "tma_info_frontend_inst_miss_cost_l2hit_percent", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Percent of instruction miss cost that hit in the L3", > > > + "MetricExpr": "100 * > > cpu_atom@MEM_BOUND_STALLS_IFETCH.LLC_HIT@ / > > cpu_atom@MEM_BOUND_STALLS_IFETCH.ALL@", > > > + "MetricName": "tma_info_frontend_inst_miss_cost_l3hit_percent", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Ratio of all branches which mispredict", > > > + "MetricExpr": "cpu_atom@BR_MISP_RETIRED.ALL_BRANCHES@ / > > BR_INST_RETIRED.ALL_BRANCHES", > > > + "MetricName": "tma_info_inst_mix_branch_mispredict_ratio", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Ratio between Mispredicted branches and > > unknown branches", > > > + "MetricExpr": "cpu_atom@BR_MISP_RETIRED.ALL_BRANCHES@ / > > BACLEARS.ANY", > > > + "MetricName": > > "tma_info_inst_mix_branch_mispredict_to_unknown_branch_ratio", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Percentage of all uops which are FPDiv uops", > > > + "MetricExpr": "100 * cpu_atom@UOPS_RETIRED.FPDIV@ / > > UOPS_RETIRED.ALL", > > > + "MetricName": "tma_info_inst_mix_fpdiv_uop_ratio", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Percentage of all uops which are IDiv uops", > > > + "MetricExpr": "100 * cpu_atom@UOPS_RETIRED.IDIV@ / > > UOPS_RETIRED.ALL", > > > + "MetricName": "tma_info_inst_mix_idiv_uop_ratio", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Instructions per Branch (lower number means > > higher occurrence rate)", > > > + "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / > > BR_INST_RETIRED.ALL_BRANCHES", > > > + "MetricName": "tma_info_inst_mix_ipbranch", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Instruction per (near) call (lower number means > > higher occurrence rate)", > > > + "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / > > BR_INST_RETIRED.NEAR_CALL", > > > + "MetricName": "tma_info_inst_mix_ipcall", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Instructions per Far Branch", > > > + "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / > > (cpu_atom@BR_INST_RETIRED.FAR_BRANCH@ / 2)", > > > + "MetricName": "tma_info_inst_mix_ipfarbranch", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Instructions per Load", > > > + "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / > > MEM_UOPS_RETIRED.ALL_LOADS", > > > + "MetricName": "tma_info_inst_mix_ipload", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Instructions per retired conditional Branch > > Misprediction where the branch was not taken", > > > + "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / > > (cpu_atom@BR_MISP_RETIRED.COND@ - > > cpu_atom@BR_MISP_RETIRED.COND_TAKEN@)", > > > + "MetricName": "tma_info_inst_mix_ipmisp_cond_ntaken", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Instructions per retired conditional Branch > > Misprediction where the branch was taken", > > > + "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / > > BR_MISP_RETIRED.COND_TAKEN", > > > + "MetricName": "tma_info_inst_mix_ipmisp_cond_taken", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Instructions per retired indirect call or jump Branch > > Misprediction", > > > + "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / > > BR_MISP_RETIRED.INDIRECT", > > > + "MetricName": "tma_info_inst_mix_ipmisp_indirect", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Instructions per retired return Branch > > Misprediction", > > > + "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / > > BR_MISP_RETIRED.RETURN", > > > + "MetricName": "tma_info_inst_mix_ipmisp_ret", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Instructions per retired Branch Misprediction", > > > + "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / > > BR_MISP_RETIRED.ALL_BRANCHES", > > > + "MetricName": "tma_info_inst_mix_ipmispredict", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Instructions per Store", > > > + "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / > > MEM_UOPS_RETIRED.ALL_STORES", > > > + "MetricName": "tma_info_inst_mix_ipstore", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Percentage of all uops which are ucode ops", > > > + "MetricExpr": "100 * cpu_atom@UOPS_RETIRED.MS@ / > > UOPS_RETIRED.ALL", > > > + "MetricName": "tma_info_inst_mix_microcode_uop_ratio", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Percentage of all uops which are x87 uops", > > > + "MetricExpr": "100 * cpu_atom@UOPS_RETIRED.X87@ / > > UOPS_RETIRED.ALL", > > > + "MetricName": "tma_info_inst_mix_x87_uop_ratio", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Percentage of total non-speculative loads with a > > address aliasing block", > > > + "MetricExpr": "100 * cpu_atom@LD_BLOCKS.ADDRESS_ALIAS@ / > > MEM_UOPS_RETIRED.ALL_LOADS", > > > + "MetricName": "tma_info_l1_bound_address_alias_blocks", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Percentage of total non-speculative loads that are > > splits", > > > + "MetricExpr": "100 * > > cpu_atom@MEM_UOPS_RETIRED.SPLIT_LOADS@ / > > MEM_UOPS_RETIRED.ALL_LOADS", > > > + "MetricName": "tma_info_l1_bound_load_splits", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Percentage of total non-speculative loads with a > > store forward or unknown store address block", > > > + "MetricExpr": "100 * cpu_atom@LD_BLOCKS.DATA_UNKNOWN@ / > > MEM_UOPS_RETIRED.ALL_LOADS", > > > + "MetricName": "tma_info_l1_bound_store_fwd_blocks", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Cycle cost per L2 hit", > > > + "MetricExpr": "cpu_atom@MEM_BOUND_STALLS_LOAD.L2_HIT@ / > > MEM_LOAD_UOPS_RETIRED.L2_HIT", > > > + "MetricName": "tma_info_memory_cycles_per_demand_load_l2_hit", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Cycle cost per LLC hit", > > > + "MetricExpr": "cpu_atom@MEM_BOUND_STALLS_LOAD.LLC_HIT@ / > > MEM_LOAD_UOPS_RETIRED.L3_HIT", > > > + "MetricName": "tma_info_memory_cycles_per_demand_load_l3_hit", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "load ops retired per 1000 instruction", > > > + "MetricExpr": "1e3 * cpu_atom@MEM_UOPS_RETIRED.ALL_LOADS@ / > > INST_RETIRED.ANY", > > > + "MetricName": "tma_info_memory_memloadpki", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Average CPU Utilization", > > > + "MetricExpr": "cpu_atom@CPU_CLK_UNHALTED.REF_TSC@ / TSC", > > > + "MetricName": "tma_info_system_cpu_utilization", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Fraction of cycles spent in Kernel mode", > > > + "MetricExpr": "cpu_atom@CPU_CLK_UNHALTED.CORE@k / > > CPU_CLK_UNHALTED.CORE", > > > + "MetricGroup": "Summary", > > > + "MetricName": "tma_info_system_kernel_utilization", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Average Frequency Utilization relative nominal > > frequency", > > > + "MetricExpr": "tma_info_core_clks / CPU_CLK_UNHALTED.REF_TSC", > > > + "MetricGroup": "Power", > > > + "MetricName": "tma_info_system_turbo_utilization", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Counts the number of issue slots that were not > > delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) > > misses.", > > > + "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.ITLB_MISS@ / > > tma_info_core_slots", > > > + "MetricGroup": > > "TopdownL3;tma_L3_group;tma_fetch_latency_group", > > > + "MetricName": "tma_itlb_misses", > > > + "MetricThreshold": "tma_itlb_misses > 0.05", > > > + "ScaleUnit": "100%", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Counts the number of cycles that the oldest load of > > the load buffer is stalled at retirement due to a load block.", > > > + "MetricExpr": "cpu_atom@LD_HEAD.L1_BOUND_AT_RET@ / > > tma_info_core_clks", > > > + "MetricGroup": > > "TopdownL3;tma_L3_group;tma_memory_bound_group", > > > + "MetricName": "tma_l1_bound", > > > + "MetricThreshold": "tma_l1_bound > 0.1", > > > + "ScaleUnit": "100%", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Counts the number of cycles a core is stalled due to > > a demand load which hit in the L2 Cache.", > > > + "MetricExpr": "cpu_atom@MEM_BOUND_STALLS_LOAD.L2_HIT@ / > > tma_info_core_clks - max((cpu_atom@MEM_BOUND_STALLS_LOAD.ALL@ - > > cpu_atom@LD_HEAD.L1_MISS_AT_RET@) / tma_info_core_clks, 0) * > > cpu_atom@MEM_BOUND_STALLS_LOAD.L2_HIT@ / > > cpu_atom@MEM_BOUND_STALLS_LOAD.ALL@", > > > + "MetricGroup": > > "TopdownL3;tma_L3_group;tma_memory_bound_group", > > > + "MetricName": "tma_l2_bound", > > > + "MetricThreshold": "tma_l2_bound > 0.1", > > > + "ScaleUnit": "100%", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Counts the number of cycles a core is stalled due to > > a demand load which hit in the Last Level Cache (LLC) or other core with > > HITE/F/M.", > > > + "MetricExpr": "cpu_atom@MEM_BOUND_STALLS_LOAD.LLC_HIT@ / > > tma_info_core_clks - max((cpu_atom@MEM_BOUND_STALLS_LOAD.ALL@ - > > cpu_atom@LD_HEAD.L1_MISS_AT_RET@) / tma_info_core_clks, 0) * > > cpu_atom@MEM_BOUND_STALLS_LOAD.LLC_HIT@ / > > cpu_atom@MEM_BOUND_STALLS_LOAD.ALL@", > > > + "MetricGroup": > > "TopdownL3;tma_L3_group;tma_memory_bound_group", > > > + "MetricName": "tma_l3_bound", > > > + "MetricThreshold": "tma_l3_bound > 0.1", > > > + "ScaleUnit": "100%", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Counts the number of cycles, relative to the > > number of mem_scheduler slots, in which uops are blocked due to load buffer > > full", > > > + "MetricExpr": "tma_mem_scheduler * > > cpu_atom@MEM_SCHEDULER_BLOCK.LD_BUF@ / > > MEM_SCHEDULER_BLOCK.ALL", > > > + "MetricGroup": > > "TopdownL4;tma_L4_group;tma_mem_scheduler_group", > > > + "MetricName": "tma_ld_buffer", > > > + "MetricThreshold": "tma_ld_buffer > 0.05", > > > + "ScaleUnit": "100%", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Counts the total number of issue slots that were > > not consumed by the backend because allocation is stalled due to a machine > > clear (nuke) of any kind including memory ordering and memory > > disambiguation.", > > > + "MetricExpr": > > "cpu_atom@TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS@ / > > tma_info_core_slots", > > > + "MetricGroup": > > "TopdownL2;tma_L2_group;tma_bad_speculation_group", > > > + "MetricName": "tma_machine_clears", > > > + "MetricThreshold": "tma_machine_clears > 0.05", > > > + "MetricgroupNoGroup": "TopdownL2", > > > + "ScaleUnit": "100%", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Counts the number of issue slots that were not > > consumed by the backend due to memory reservation stalls in which a > > scheduler is not able to accept uops.", > > > + "MetricExpr": > > "cpu_atom@TOPDOWN_BE_BOUND.MEM_SCHEDULER@ / > > tma_info_core_slots", > > > + "MetricGroup": > > "TopdownL3;tma_L3_group;tma_resource_bound_group", > > > + "MetricName": "tma_mem_scheduler", > > > + "MetricThreshold": "tma_mem_scheduler > 0.1", > > > + "ScaleUnit": "100%", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Counts the number of cycles the core is stalled due > > to stores or loads.", > > > + "MetricExpr": "min(tma_backend_bound, > > cpu_atom@LD_HEAD.ANY_AT_RET@ / tma_info_core_clks + > > tma_store_bound)", > > > + "MetricGroup": > > "TopdownL2;tma_L2_group;tma_backend_bound_group", > > > + "MetricName": "tma_memory_bound", > > > + "MetricThreshold": "tma_memory_bound > 0.2", > > > + "MetricgroupNoGroup": "TopdownL2", > > > + "ScaleUnit": "100%", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Counts the number of machine clears relative to > > the number of nuke slots due to memory ordering.", > > > + "MetricExpr": "tma_nuke * > > (cpu_atom@MACHINE_CLEARS.MEMORY_ORDERING@ / > > cpu_atom@MACHINE_CLEARS.SLOW@)", > > > + "MetricGroup": "TopdownL4;tma_L4_group;tma_nuke_group", > > > + "MetricName": "tma_memory_ordering", > > > + "MetricThreshold": "tma_memory_ordering > 0.02", > > > + "ScaleUnit": "100%", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Counts the number of uops that are from the > > complex flows issued by the micro-sequencer (MS)", > > > + "MetricExpr": "cpu_atom@UOPS_RETIRED.MS@ / > > tma_info_core_slots", > > > + "MetricGroup": "TopdownL2;tma_L2_group;tma_retiring_group", > > > + "MetricName": "tma_ms_uops", > > > + "MetricThreshold": "tma_ms_uops > 0.05", > > > + "MetricgroupNoGroup": "TopdownL2", > > > + "PublicDescription": "Counts the number of uops that are from the > > complex flows issued by the micro-sequencer (MS). This includes uops from > > flows due to complex instructions, faults, assists, and inserted flows.", > > > + "ScaleUnit": "100%", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Counts the number of issue slots that were not > > consumed by the backend due to IEC or FPC RAT stalls, which can be due to > > FIQ or IEC reservation stalls in which the integer, floating point or SIMD > > scheduler is not able to accept uops.", > > > + "MetricExpr": > > "cpu_atom@TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER@ / > > tma_info_core_slots", > > > + "MetricGroup": > > "TopdownL3;tma_L3_group;tma_resource_bound_group", > > > + "MetricName": "tma_non_mem_scheduler", > > > + "MetricThreshold": "tma_non_mem_scheduler > 0.1", > > > + "ScaleUnit": "100%", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Counts the number of issue slots that were not > > consumed by the backend due to a machine clear (slow nuke).", > > > + "MetricExpr": "cpu_atom@TOPDOWN_BAD_SPECULATION.NUKE@ / > > tma_info_core_slots", > > > + "MetricGroup": > > "TopdownL3;tma_L3_group;tma_machine_clears_group", > > > + "MetricName": "tma_nuke", > > > + "MetricThreshold": "tma_nuke > 0.05", > > > + "ScaleUnit": "100%", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Counts the number of issue slots that were not > > delivered by the frontend due to other common frontend stalls not > > categorized.", > > > + "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.OTHER@ / > > tma_info_core_slots", > > > + "MetricGroup": > > "TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", > > > + "MetricName": "tma_other_fb", > > > + "MetricThreshold": "tma_other_fb > 0.05", > > > + "ScaleUnit": "100%", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Counts the number of cycles that the oldest load of > > the load buffer is stalled at retirement due to a number of other load blocks.", > > > + "MetricExpr": "cpu_atom@LD_HEAD.OTHER_AT_RET@ / > > tma_info_core_clks", > > > + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", > > > + "MetricName": "tma_other_l1", > > > + "MetricThreshold": "tma_other_l1 > 0.05", > > > + "ScaleUnit": "100%", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Counts the number of cycles the core is stalled due > > to a demand load miss which hits in the L2, LLC, DRAM or MMIO (Non-DRAM) > > but could not be correctly attributed or cycles in which the load miss is waiting > > on a request buffer.", > > > + "MetricExpr": "max(0, tma_memory_bound - (tma_store_bound + > > tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound))", > > > + "MetricGroup": > > "TopdownL3;tma_L3_group;tma_memory_bound_group", > > > + "MetricName": "tma_other_load_store", > > > + "MetricThreshold": "tma_other_load_store > 0.1", > > > + "ScaleUnit": "100%", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Counts the number of uops retired excluding ms > > and fp div uops.", > > > + "MetricExpr": "(cpu_atom@TOPDOWN_RETIRING.ALL@ - > > cpu_atom@UOPS_RETIRED.MS@ - cpu_atom@UOPS_RETIRED.FPDIV@) / > > tma_info_core_slots", > > > + "MetricGroup": "TopdownL3;tma_L3_group;tma_base_group", > > > + "MetricName": "tma_other_ret", > > > + "MetricThreshold": "tma_other_ret > 0.3", > > > + "ScaleUnit": "100%", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Counts the number of machine clears relative to > > the number of nuke slots due to page faults.", > > > + "MetricExpr": "tma_nuke * > > (cpu_atom@MACHINE_CLEARS.PAGE_FAULT@ / > > cpu_atom@MACHINE_CLEARS.SLOW@)", > > > + "MetricGroup": "TopdownL4;tma_L4_group;tma_nuke_group", > > > + "MetricName": "tma_page_fault", > > > + "MetricThreshold": "tma_page_fault > 0.02", > > > + "ScaleUnit": "100%", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Counts the number of issue slots that were not > > delivered by the frontend due to wrong predecodes.", > > > + "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.PREDECODE@ / > > tma_info_core_slots", > > > + "MetricGroup": > > "TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", > > > + "MetricName": "tma_predecode", > > > + "MetricThreshold": "tma_predecode > 0.05", > > > + "ScaleUnit": "100%", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Counts the number of issue slots that were not > > consumed by the backend due to the physical register file unable to accept an > > entry (marble stalls).", > > > + "MetricExpr": "cpu_atom@TOPDOWN_BE_BOUND.REGISTER@ / > > tma_info_core_slots", > > > + "MetricGroup": > > "TopdownL3;tma_L3_group;tma_resource_bound_group", > > > + "MetricName": "tma_register", > > > + "MetricThreshold": "tma_register > 0.1", > > > + "ScaleUnit": "100%", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Counts the number of issue slots that were not > > consumed by the backend due to the reorder buffer being full (ROB stalls).", > > > + "MetricExpr": > > "cpu_atom@TOPDOWN_BE_BOUND.REORDER_BUFFER@ / > > tma_info_core_slots", > > > + "MetricGroup": > > "TopdownL3;tma_L3_group;tma_resource_bound_group", > > > + "MetricName": "tma_reorder_buffer", > > > + "MetricThreshold": "tma_reorder_buffer > 0.1", > > > + "ScaleUnit": "100%", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Counts the total number of issue slots that were > > not consumed by the backend due to backend stalls", > > > + "MetricExpr": "tma_backend_bound", > > > + "MetricGroup": > > "TopdownL2;tma_L2_group;tma_backend_bound_aux_group", > > > + "MetricName": "tma_resource_bound", > > > + "MetricThreshold": "tma_resource_bound > 0.2", > > > + "MetricgroupNoGroup": "TopdownL2", > > > + "PublicDescription": "Counts the total number of issue slots that were > > not consumed by the backend due to backend stalls. Note that uops must be > > available for consumption in order for this event to count. If a uop is not > > available (IQ is empty), this event will not count.", > > > + "ScaleUnit": "100%", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Counts the number of issue slots that result in > > retirement slots.", > > > + "MetricExpr": "cpu_atom@TOPDOWN_RETIRING.ALL@ / > > tma_info_core_slots", > > > + "MetricGroup": "TopdownL1;tma_L1_group", > > > + "MetricName": "tma_retiring", > > > + "MetricThreshold": "tma_retiring > 0.75", > > > + "MetricgroupNoGroup": "TopdownL1", > > > + "ScaleUnit": "100%", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Counts the number of cycles, relative to the > > number of mem_scheduler slots, in which uops are blocked due to RSV full > > relative", > > > + "MetricExpr": "tma_mem_scheduler * > > cpu_atom@MEM_SCHEDULER_BLOCK.RSV@ / > > MEM_SCHEDULER_BLOCK.ALL", > > > + "MetricGroup": > > "TopdownL4;tma_L4_group;tma_mem_scheduler_group", > > > + "MetricName": "tma_rsv", > > > + "MetricThreshold": "tma_rsv > 0.05", > > > + "ScaleUnit": "100%", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Counts the number of issue slots that were not > > consumed by the backend due to scoreboards from the instruction queue > > (IQ), jump execution unit (JEU), or microcode sequencer (MS).", > > > + "MetricExpr": "cpu_atom@TOPDOWN_BE_BOUND.SERIALIZATION@ / > > tma_info_core_slots", > > > + "MetricGroup": > > "TopdownL3;tma_L3_group;tma_resource_bound_group", > > > + "MetricName": "tma_serialization", > > > + "MetricThreshold": "tma_serialization > 0.1", > > > + "ScaleUnit": "100%", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Counts the number of machine clears relative to > > the number of nuke slots due to SMC.", > > > + "MetricExpr": "tma_nuke * (cpu_atom@MACHINE_CLEARS.SMC@ / > > cpu_atom@MACHINE_CLEARS.SLOW@)", > > > + "MetricGroup": "TopdownL4;tma_L4_group;tma_nuke_group", > > > + "MetricName": "tma_smc", > > > + "MetricThreshold": "tma_smc > 0.02", > > > + "ScaleUnit": "100%", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Counts the number of cycles, relative to the > > number of mem_scheduler slots, in which uops are blocked due to store buffer > > full", > > > + "MetricExpr": "tma_store_bound", > > > + "MetricGroup": > > "TopdownL4;tma_L4_group;tma_mem_scheduler_group", > > > + "MetricName": "tma_st_buffer", > > > + "MetricThreshold": "tma_st_buffer > 0.05", > > > + "ScaleUnit": "100%", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Counts the number of cycles that the oldest load of > > the load buffer is stalled at retirement due to a first level TLB miss.", > > > + "MetricExpr": "cpu_atom@LD_HEAD.DTLB_MISS_AT_RET@ / > > tma_info_core_clks", > > > + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", > > > + "MetricName": "tma_stlb_hit", > > > + "MetricThreshold": "tma_stlb_hit > 0.05", > > > + "ScaleUnit": "100%", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Counts the number of cycles that the oldest load of > > the load buffer is stalled at retirement due to a second level TLB miss requiring > > a page walk.", > > > + "MetricExpr": "cpu_atom@LD_HEAD.PGWALK_AT_RET@ / > > tma_info_core_clks", > > > + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", > > > + "MetricName": "tma_stlb_miss", > > > + "MetricThreshold": "tma_stlb_miss > 0.05", > > > + "ScaleUnit": "100%", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Counts the number of cycles the core is stalled due > > to store buffer full.", > > > + "MetricExpr": "tma_mem_scheduler * > > (cpu_atom@MEM_SCHEDULER_BLOCK.ST_BUF@ / > > cpu_atom@MEM_SCHEDULER_BLOCK.ALL@)", > > > + "MetricGroup": > > "TopdownL3;tma_L3_group;tma_memory_bound_group", > > > + "MetricName": "tma_store_bound", > > > + "MetricThreshold": "tma_store_bound > 0.1", > > > + "ScaleUnit": "100%", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Counts the number of cycles that the oldest load of > > the load buffer is stalled at retirement due to a store forward block.", > > > + "MetricExpr": "cpu_atom@LD_HEAD.ST_ADDR_AT_RET@ / > > tma_info_core_clks", > > > + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", > > > + "MetricName": "tma_store_fwd_blk", > > > + "MetricThreshold": "tma_store_fwd_blk > 0.05", > > > + "ScaleUnit": "100%", > > > + "Unit": "cpu_atom" > > > + }, > > > + { > > > + "BriefDescription": "Uncore frequency per die [GHZ]", > > > + "MetricExpr": "tma_info_system_socket_clks / #num_dies / > > duration_time / 1e9", > > > + "MetricGroup": "SoC", > > > + "MetricName": "UNCORE_FREQ", > > > + "Unit": "cpu_core" > > > + }, > > > + { > > > + "BriefDescription": "This metric represents Core fraction of cycles CPU > > dispatched uops on execution ports for ALU operations.", > > > + "MetricExpr": "(cpu_core@UOPS_DISPATCHED.PORT_0@ + > > cpu_core@UOPS_DISPATCHED.PORT_1@ + > > cpu_core@UOPS_DISPATCHED.PORT_5_11@ + > > cpu_core@UOPS_DISPATCHED.PORT_6@) / (5 * tma_info_core_core_clks)", > > > + "MetricGroup": > > "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", > > > + "MetricName": "tma_alu_op_utilization", > > > + "MetricThreshold": "tma_alu_op_utilization > 0.4", > > > + "ScaleUnit": "100%", > > > + "Unit": "cpu_core" > > > + }, > > > + { > > > + "BriefDescription": "This metric estimates fraction of slots the CPU > > retired uops delivered by the Microcode_Sequencer as a result of Assists", > > > + "MetricExpr": "78 * cpu_core@ASSISTS.ANY@ / > > tma_info_thread_slots", > > > + "MetricGroup": > > "TopdownL4;tma_L4_group;tma_microcode_sequencer_group", > > > + "MetricName": "tma_assists", > > > + "MetricThreshold": "tma_assists > 0.1 & (tma_microcode_sequencer > > > 0.05 & tma_heavy_operations > 0.1)", > > > + "PublicDescription": "This metric estimates fraction of slots the CPU > > retired uops delivered by the Microcode_Sequencer as a result of Assists. > > Assists are long sequences of uops that are required in certain corner-cases for > > operations that cannot be handled natively by the execution pipeline. For > > example; when working with very small floating point values (so-called > > Denormals); the FP units are not set up to perform these operations natively. > > Instead; a sequence of instructions to perform the computation on the > > Denormals is injected into the pipeline. Since these microcode sequences > > might be dozens of uops long; Assists can be extremely deleterious to > > performance and they can be avoided in many cases. Sample with: > > ASSISTS.ANY", > > > + "ScaleUnit": "100%", > > > + "Unit": "cpu_core" > > > + }, > > > + { > > > + "BriefDescription": "This metric estimates fraction of slots the CPU > > retired uops as a result of handing SSE to AVX* or AVX* to SSE transition > > Assists.", > > > + "MetricExpr": "63 * cpu_core@ASSISTS.SSE_AVX_MIX@ / > > tma_info_thread_slots", > > > + "MetricGroup": "HPC;TopdownL5;tma_L5_group;tma_assists_group", > > > + "MetricName": "tma_avx_assists", > > > + "MetricThreshold": "tma_avx_assists > 0.1", > > > + "ScaleUnit": "100%", > > > + "Unit": "cpu_core" > > > + }, > > > + { > > > + "BriefDescription": "This category represents fraction of slots where no > > uops are being delivered due to a lack of required resources for accepting new > > uops in the Backend", > > > + "MetricExpr": "cpu_core@topdown\\-be\\-bound@ / > > (cpu_core@topdown\\-fe\\-bound@ + cpu_core@topdown\\-bad\\-spec@ > > + cpu_core@topdown\\-retiring@ + cpu_core@topdown\\-be\\-bound@) + > > 0 * tma_info_thread_slots", > > > + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", > > > + "MetricName": "tma_backend_bound", > > > + "MetricThreshold": "tma_backend_bound > 0.2", > > > + "MetricgroupNoGroup": "TopdownL1", > > > + "PublicDescription": "This category represents fraction of slots where > > no uops are being delivered due to a lack of required resources for accepting > > new uops in the Backend. Backend is the portion of the processor core where > > the out-of-order scheduler dispatches ready uops into their respective > > execution units; and once completed these uops get retired according to > > program order. For example; stalls due to data-cache misses or stalls due to > > the divider unit being overloaded are both categorized under Backend Bound. > > Backend Bound is further divided into two main categories: Memory Bound > > and Core Bound. Sample with: TOPDOWN.BACKEND_BOUND_SLOTS", > > > + "ScaleUnit": "100%", > > > + "Unit": "cpu_core" > > > + }, > > > + { > > > + "BriefDescription": "This category represents fraction of slots wasted > > due to incorrect speculations", > > > + "MetricExpr": "max(1 - (tma_frontend_bound + tma_backend_bound + > > tma_retiring), 0)", > > > + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", > > > + "MetricName": "tma_bad_speculation", > > > + "MetricThreshold": "tma_bad_speculation > 0.15", > > > + "MetricgroupNoGroup": "TopdownL1", > > > + "PublicDescription": "This category represents fraction of slots wasted > > due to incorrect speculations. This include slots used to issue uops that do not > > eventually get retired and slots for which the issue-pipeline was blocked due to > > recovery from earlier incorrect speculation. For example; wasted work due to > > miss-predicted branches are categorized under Bad Speculation category. > > Incorrect data speculation followed by Memory Ordering Nukes is another > > example.", > > > + "ScaleUnit": "100%", > > > + "Unit": "cpu_core" > > > + }, > > > + { > > > + "BriefDescription": "This metric represents fraction of slots the CPU has > > wasted due to Branch Misprediction", > > > + "MetricExpr": "cpu_core@topdown\\-br\\-mispredict@ / > > (cpu_core@topdown\\-fe\\-bound@ + cpu_core@topdown\\-bad\\-spec@ > > + cpu_core@topdown\\-retiring@ + cpu_core@topdown\\-be\\-bound@) + > > 0 * tma_info_thread_slots", > > > + "MetricGroup": > > "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group;tma_bad_specula > > tion_group;tma_issueBM", > > > + "MetricName": "tma_branch_mispredicts", > > > + "MetricThreshold": "tma_branch_mispredicts > 0.1 & > > tma_bad_speculation > 0.15", > > > + "MetricgroupNoGroup": "TopdownL2", > > > + "PublicDescription": "This metric represents fraction of slots the CPU > > has wasted due to Branch Misprediction. These slots are either wasted by > > uops fetched from an incorrectly speculated program path; or stalls when the > > out-of-order part of the machine needs to recover its state from a speculative > > path. Sample with: TOPDOWN.BR_MISPREDICT_SLOTS. Related metrics: > > tma_info_bad_spec_branch_misprediction_cost, > > tma_info_bottleneck_mispredictions, tma_mispredicts_resteers", > > > + "ScaleUnit": "100%", > > > + "Unit": "cpu_core" > > > + }, > > > + { > > > + "BriefDescription": "This metric represents fraction of cycles the CPU > > was stalled due to Branch Resteers", > > > + "MetricExpr": "cpu_core@INT_MISC.CLEAR_RESTEER_CYCLES@ / > > tma_info_thread_clks + tma_unknown_branches", > > > + "MetricGroup": > > "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group", > > > + "MetricName": "tma_branch_resteers", > > > + "MetricThreshold": "tma_branch_resteers > 0.05 & > > (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", > > > + "PublicDescription": "This metric represents fraction of cycles the CPU > > was stalled due to Branch Resteers. Branch Resteers estimates the Frontend > > delay in fetching operations from corrected path; following all sorts of miss- > > predicted branches. For example; branchy code with lots of miss-predictions > > might get categorized under Branch Resteers. Note the value of this node may > > overlap with its siblings. Sample with: BR_MISP_RETIRED.ALL_BRANCHES", > > > + "ScaleUnit": "100%", > > > + "Unit": "cpu_core" > > > + }, > > > + { > > > + "BriefDescription": "This metric represents fraction of cycles the CPU > > was stalled due staying in C0.1 power-performance optimized state (Faster > > wakeup time; Smaller power savings).", > > > + "MetricExpr": "cpu_core@CPU_CLK_UNHALTED.C01@ / > > tma_info_thread_clks", > > > + "MetricGroup": > > "C0Wait;TopdownL4;tma_L4_group;tma_serializing_operation_group", > > > + "MetricName": "tma_c01_wait", > > > + "MetricThreshold": "tma_c01_wait > 0.05 & > > (tma_serializing_operation > 0.1 & (tma_core_bound > 0.1 & > > tma_backend_bound > 0.2))", > > > + "ScaleUnit": "100%", > > > + "Unit": "cpu_core" > > > + }, > > > + { > > > + "BriefDescription": "This metric represents fraction of cycles the CPU > > was stalled due staying in C0.2 power-performance optimized state (Slower > > wakeup time; Larger power savings).", > > > + "MetricExpr": "cpu_core@CPU_CLK_UNHALTED.C02@ / > > tma_info_thread_clks", > > > + "MetricGroup": > > "C0Wait;TopdownL4;tma_L4_group;tma_serializing_operation_group", > > > + "MetricName": "tma_c02_wait", > > > + "MetricThreshold": "tma_c02_wait > 0.05 & > > (tma_serializing_operation > 0.1 & (tma_core_bound > 0.1 & > > tma_backend_bound > 0.2))", > > > + "ScaleUnit": "100%", > > > + "Unit": "cpu_core" > > > + }, > > > + { > > > + "BriefDescription": "This metric estimates fraction of cycles the CPU > > retired uops originated from CISC (complex instruction set computer) > > instruction", > > > + "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)", > > > + "MetricGroup": > > "TopdownL4;tma_L4_group;tma_microcode_sequencer_group", > > > + "MetricName": "tma_cisc", > > > + "MetricThreshold": "tma_cisc > 0.1 & (tma_microcode_sequencer > > > 0.05 & tma_heavy_operations > 0.1)", > > > + "PublicDescription": "This metric estimates fraction of cycles the CPU > > retired uops originated from CISC (complex instruction set computer) > > instruction. A CISC instruction has multiple uops that are required to perform > > the instruction's functionality as in the case of read-modify-write as an > > example. Since these instructions require multiple uops they may or may not > > imply sub-optimal use of machine resources. Sample with: > > FRONTEND_RETIRED.MS_FLOWS", > > > + "ScaleUnit": "100%", > > > + "Unit": "cpu_core" > > > + }, > > > + { > > > + "BriefDescription": "This metric represents fraction of cycles the CPU > > was stalled due to Branch Resteers as a result of Machine Clears", > > > + "MetricExpr": "(1 - tma_branch_mispredicts / tma_bad_speculation) * > > cpu_core@INT_MISC.CLEAR_RESTEER_CYCLES@ / tma_info_thread_clks", > > > + "MetricGroup": > > "BadSpec;MachineClears;TopdownL4;tma_L4_group;tma_branch_resteers_gr > > oup;tma_issueMC", > > > + "MetricName": "tma_clears_resteers", > > > + "MetricThreshold": "tma_clears_resteers > 0.05 & > > (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & > > tma_frontend_bound > 0.15))", > > > + "PublicDescription": "This metric represents fraction of cycles the CPU > > was stalled due to Branch Resteers as a result of Machine Clears. Sample with: > > INT_MISC.CLEAR_RESTEER_CYCLES. Related metrics: tma_l1_bound, > > tma_machine_clears, tma_microcode_sequencer, tma_ms_switches", > > > + "ScaleUnit": "100%", > > > + "Unit": "cpu_core" > > > + }, > > > + { > > > + "BriefDescription": "This metric estimates fraction of cycles while the > > memory subsystem was handling synchronizations due to contested > > accesses", > > > + "MetricExpr": > > "(cpu_core@MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS@ * > > min(cpu_core@MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS@:retire_latency, > > 24 * tma_info_system_core_frequency) + > > cpu_core@MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD@ * > > min(cpu_core@MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD@:retire_latency, 25 > > * tma_info_system_core_frequency) * > > (cpu_core@OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM@ / > > (cpu_core@OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM@ + > > cpu_core@OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD@))) * (1 > > + cpu_core@MEM_LOAD_RETIRED.FB_HIT@ / > > cpu_core@MEM_LOAD_RETIRED.L1_MISS@ / 2) / tma_info_thread_clks", > > > > Thanks Weilin! The modifier on an event doesn't usually have the colon > > when there is a slash. So: > > cpu_core@MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD@:retire_latency > > Should be: > > cpu_core@MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD@retire_latency > Thanks Ian! I will update this accordingly. > > > The modifiers also tend to be a single character. The modifier 'R' is > > unused, so I wonder we can use it here so that we can support these > > events not just in metrics. > Do you mean we use 'R' instead of "retire_latency" in all the formulas? I could do this > Update. I think 'R' is more consistent with all the other event modifiers, but I also like that your name is intention revealing. I think as we work this into a more architecture neutral thing it is likely we'll want retirement latency to just be like an event, in which case the modifier could be combined with other modifiers. So MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD:uR could mean the MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD event with retirement latency only sampled in user land. Somebody may have a different preference on which letter, but R doesn't look unreasonable to me. Thanks, Ian > > > > Ian > ^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2024-02-29 2:01 UTC | newest] Thread overview: 10+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2024-02-28 16:12 [RFC PATCH v2 0/6] TPEBS counting mode support weilin.wang 2024-02-28 16:12 ` [RFC PATCH v2 1/6] perf stat: Parse and find tpebs events when parsing metrics to prepare for perf record sampling weilin.wang 2024-02-28 16:12 ` [RFC PATCH v2 2/6] perf stat: Fork and launch perf record when perf stat needs to get retire latency value for a metric weilin.wang 2024-02-28 16:12 ` [RFC PATCH v2 3/6] perf stat: Add retire latency values into the expr_parse_ctx to prepare for final metric calculation weilin.wang 2024-02-28 16:12 ` [RFC PATCH v2 4/6] perf stat: Create another thread for sample data processing weilin.wang 2024-02-28 16:12 ` [RFC PATCH v2 5/6] perf stat: Add retire latency print functions to print out at the very end of print out weilin.wang 2024-02-28 16:12 ` [RFC PATCH v2 6/6] perf vendor events intel: Add MTL metric json files weilin.wang 2024-02-28 16:50 ` Ian Rogers 2024-02-29 1:36 ` Wang, Weilin 2024-02-29 2:01 ` Ian Rogers
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