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From: Ian Rogers <irogers@google.com>
To: Perry Taylor <perry.taylor@intel.com>,
	Samantha Alt <samantha.alt@intel.com>,
	 Caleb Biggers <caleb.biggers@intel.com>,
	Weilin Wang <weilin.wang@intel.com>,
	 Edward Baker <edward.baker@intel.com>,
	Peter Zijlstra <peterz@infradead.org>,
	 Ingo Molnar <mingo@redhat.com>,
	Arnaldo Carvalho de Melo <acme@kernel.org>,
	Namhyung Kim <namhyung@kernel.org>,
	 Mark Rutland <mark.rutland@arm.com>,
	 Alexander Shishkin <alexander.shishkin@linux.intel.com>,
	Jiri Olsa <jolsa@kernel.org>,  Ian Rogers <irogers@google.com>,
	Adrian Hunter <adrian.hunter@intel.com>,
	 James Clark <james.clark@arm.com>,
	John Garry <john.g.garry@oracle.com>,
	 linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org,
	 Stephane Eranian <eranian@google.com>
Subject: [PATCH v3 10/20] perf jevents: Add load store breakdown metrics ldst for Intel
Date: Wed, 13 Mar 2024 22:59:09 -0700	[thread overview]
Message-ID: <20240314055919.1979781-11-irogers@google.com> (raw)
In-Reply-To: <20240314055919.1979781-1-irogers@google.com>

Give breakdown of number of instructions. Use the counter mask (cmask)
to show the number of cycles taken to retire the instructions.

Signed-off-by: Ian Rogers <irogers@google.com>
---
 tools/perf/pmu-events/intel_metrics.py | 86 +++++++++++++++++++++++++-
 1 file changed, 85 insertions(+), 1 deletion(-)

diff --git a/tools/perf/pmu-events/intel_metrics.py b/tools/perf/pmu-events/intel_metrics.py
index 9ef30e5d3e25..4ac419212b3d 100755
--- a/tools/perf/pmu-events/intel_metrics.py
+++ b/tools/perf/pmu-events/intel_metrics.py
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: (LGPL-2.1 OR BSD-2-Clause)
 from metric import (d_ratio, has_event, max, CheckPmu, Event, JsonEncodeMetric,
                     JsonEncodeMetricGroupDescriptions, Literal, LoadEvents,
-                    Metric, MetricGroup, MetricRef, Select)
+                    Metric, MetricConstraint, MetricGroup, MetricRef, Select)
 import argparse
 import json
 import math
@@ -508,6 +508,89 @@ def IntelSwpf() -> Optional[MetricGroup]:
   ], description="Sofware prefetch instruction breakdown")
 
 
+def IntelLdSt() -> Optional[MetricGroup]:
+  if _args.model in [
+      "bonnell",
+      "nehalemep",
+      "nehalemex",
+      "westmereep-dp",
+      "westmereep-sp",
+      "westmereex",
+  ]:
+    return None
+  LDST_LD = Event("MEM_INST_RETIRED.ALL_LOADS", "MEM_UOPS_RETIRED.ALL_LOADS")
+  LDST_ST = Event("MEM_INST_RETIRED.ALL_STORES", "MEM_UOPS_RETIRED.ALL_STORES")
+  LDST_LDC1 = Event(f"{LDST_LD.name}/cmask=1/")
+  LDST_STC1 = Event(f"{LDST_ST.name}/cmask=1/")
+  LDST_LDC2 = Event(f"{LDST_LD.name}/cmask=2/")
+  LDST_STC2 = Event(f"{LDST_ST.name}/cmask=2/")
+  LDST_LDC3 = Event(f"{LDST_LD.name}/cmask=3/")
+  LDST_STC3 = Event(f"{LDST_ST.name}/cmask=3/")
+  ins = Event("instructions")
+  LDST_CYC = Event("CPU_CLK_UNHALTED.THREAD",
+                   "CPU_CLK_UNHALTED.CORE_P",
+                   "CPU_CLK_UNHALTED.THREAD_P")
+  LDST_PRE = None
+  try:
+    LDST_PRE = Event("LOAD_HIT_PREFETCH.SWPF", "LOAD_HIT_PRE.SW_PF")
+  except:
+    pass
+  LDST_AT = None
+  try:
+    LDST_AT = Event("MEM_INST_RETIRED.LOCK_LOADS")
+  except:
+    pass
+  cyc  = LDST_CYC
+
+  ld_rate = d_ratio(LDST_LD, interval_sec)
+  st_rate = d_ratio(LDST_ST, interval_sec)
+  pf_rate = d_ratio(LDST_PRE, interval_sec) if LDST_PRE else None
+  at_rate = d_ratio(LDST_AT, interval_sec) if LDST_AT else None
+
+  ldst_ret_constraint = MetricConstraint.GROUPED_EVENTS
+  if LDST_LD.name == "MEM_UOPS_RETIRED.ALL_LOADS":
+    ldst_ret_constraint = MetricConstraint.NO_GROUP_EVENTS_NMI
+
+  return MetricGroup("ldst", [
+      MetricGroup("ldst_total", [
+          Metric("ldst_total_loads", "Load/store instructions total loads",
+                 ld_rate, "loads"),
+          Metric("ldst_total_stores", "Load/store instructions total stores",
+                 st_rate, "stores"),
+      ]),
+      MetricGroup("ldst_prcnt", [
+          Metric("ldst_prcnt_loads", "Percent of all instructions that are loads",
+                 d_ratio(LDST_LD, ins), "100%"),
+          Metric("ldst_prcnt_stores", "Percent of all instructions that are stores",
+                 d_ratio(LDST_ST, ins), "100%"),
+      ]),
+      MetricGroup("ldst_ret_lds", [
+          Metric("ldst_ret_lds_1", "Retired loads in 1 cycle",
+                 d_ratio(max(LDST_LDC1 - LDST_LDC2, 0), cyc), "100%",
+                 constraint = ldst_ret_constraint),
+          Metric("ldst_ret_lds_2", "Retired loads in 2 cycles",
+                 d_ratio(max(LDST_LDC2 - LDST_LDC3, 0), cyc), "100%",
+                 constraint = ldst_ret_constraint),
+          Metric("ldst_ret_lds_3", "Retired loads in 3 or more cycles",
+                 d_ratio(LDST_LDC3, cyc), "100%"),
+      ]),
+      MetricGroup("ldst_ret_sts", [
+          Metric("ldst_ret_sts_1", "Retired stores in 1 cycle",
+                 d_ratio(max(LDST_STC1 - LDST_STC2, 0), cyc), "100%",
+                 constraint = ldst_ret_constraint),
+          Metric("ldst_ret_sts_2", "Retired stores in 2 cycles",
+                 d_ratio(max(LDST_STC2 - LDST_STC3, 0), cyc), "100%",
+                 constraint = ldst_ret_constraint),
+          Metric("ldst_ret_sts_3", "Retired stores in 3 more cycles",
+                 d_ratio(LDST_STC3, cyc), "100%"),
+      ]),
+      Metric("ldst_ld_hit_swpf", "Load hit software prefetches per second",
+             pf_rate, "swpf/s") if pf_rate else None,
+      Metric("ldst_atomic_lds", "Atomic loads per second",
+             at_rate, "loads/s") if at_rate else None,
+  ], description = "Breakdown of load/store instructions")
+
+
 def main() -> None:
   global _args
 
@@ -537,6 +620,7 @@ def main() -> None:
       Tsx(),
       IntelBr(),
       IntelL2(),
+      IntelLdSt(),
       IntelPorts(),
       IntelSwpf(),
   ])
-- 
2.44.0.278.ge034bb2e1d-goog


  parent reply	other threads:[~2024-03-14  5:59 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-03-14  5:58 [PATCH v3 00/20] Python generated Intel metrics Ian Rogers
2024-03-14  5:59 ` [PATCH v3 01/20] perf jevents: Add RAPL metrics for all Intel models Ian Rogers
2024-03-14  5:59 ` [PATCH v3 02/20] perf jevents: Add idle metric for " Ian Rogers
2024-03-14  5:59 ` [PATCH v3 03/20] perf jevents: Add smi metric group " Ian Rogers
2024-03-14  5:59 ` [PATCH v3 04/20] perf jevents: Add CheckPmu to see if a PMU is in loaded json events Ian Rogers
2024-03-14  5:59 ` [PATCH v3 05/20] perf jevents: Add tsx metric group for Intel models Ian Rogers
2024-03-14  5:59 ` [PATCH v3 06/20] perf jevents: Add br metric group for branch statistics on Intel Ian Rogers
2024-03-14  5:59 ` [PATCH v3 07/20] perf jevents: Add software prefetch (swpf) metric group for Intel Ian Rogers
2024-03-14  5:59 ` [PATCH v3 08/20] perf jevents: Add ports metric group giving utilization on Intel Ian Rogers
2024-03-14  5:59 ` [PATCH v3 09/20] perf jevents: Add L2 metrics for Intel Ian Rogers
2024-03-14  5:59 ` Ian Rogers [this message]
2024-03-14  5:59 ` [PATCH v3 11/20] perf jevents: Add ILP " Ian Rogers
2024-03-14  5:59 ` [PATCH v3 12/20] perf jevents: Add context switch " Ian Rogers
2024-03-14  5:59 ` [PATCH v3 13/20] perf jevents: Add FPU " Ian Rogers
2024-03-14  5:59 ` [PATCH v3 14/20] perf jevents: Add Miss Level Parallelism (MLP) metric " Ian Rogers
2024-03-14  5:59 ` [PATCH v3 15/20] perf jevents: Add mem_bw " Ian Rogers
2024-03-14  5:59 ` [PATCH v3 16/20] perf jevents: Add local/remote "mem" breakdown metrics " Ian Rogers
2024-03-14  5:59 ` [PATCH v3 17/20] perf jevents: Add dir " Ian Rogers
2024-03-14  5:59 ` [PATCH v3 18/20] perf jevents: Add C-State metrics from the PCU PMU " Ian Rogers
2024-03-14  5:59 ` [PATCH v3 19/20] perf jevents: Add local/remote miss latency metrics " Ian Rogers
2024-03-14  5:59 ` [PATCH v3 20/20] perf jevents: Add upi_bw metric " Ian Rogers

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