From: Tanmay Jagdale <tanmay@marvell.com>
To: <john.g.garry@oracle.com>, <will@kernel.org>,
<james.clark@arm.com>, <mike.leach@linaro.org>,
<leo.yan@linux.dev>, <suzuki.poulose@arm.com>,
<peterz@infradead.org>, <mingo@redhat.com>,
<alexander.shishkin@linux.intel.com>, <jolsa@kernel.org>,
<irogers@google.com>, <adrian.hunter@intel.com>
Cc: <linux-arm-kernel@lists.infradead.org>,
<coresight@lists.linaro.org>, <linux-perf-users@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <sgoutham@marvell.com>,
<gcherian@marvell.com>, <lcherian@marvell.com>,
Tanmay Jagdale <tanmay@marvell.com>
Subject: [PATCH V2 1/2] perf: cs-etm: Fixes in instruction sample synthesis
Date: Thu, 4 Apr 2024 23:37:30 +0530 [thread overview]
Message-ID: <20240404180731.7006-2-tanmay@marvell.com> (raw)
In-Reply-To: <20240404180731.7006-1-tanmay@marvell.com>
The existing method of synthesizing instruction samples has the
following issues:
1. Branch target address is missing.
2. Non-branch instructions have mnemonics of branch instructions.
To fix issue 1), start synthesizing the instructions from the
previous packet (tidq->prev_packet) instead of current packet
(tidq->packet). This way, it is easy to figure out the target
address of the branch instruction in tidq->prev_packet which
is the current packet's (tidq->packet) first executed instruction.
After the switch to processing the previous packet first, we no
longer need to swap the packets during cs_etm__flush()
Fix for issue 2) is to set the sample flags only when we reach the
last instruction in the tidq (which would be a branch instruction).
Signed-off-by: Tanmay Jagdale <tanmay@marvell.com>
---
tools/perf/util/cs-etm.c | 32 +++++++++++++++++++++++++-------
1 file changed, 25 insertions(+), 7 deletions(-)
diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c
index d65d7485886c..55db1932f785 100644
--- a/tools/perf/util/cs-etm.c
+++ b/tools/perf/util/cs-etm.c
@@ -1493,10 +1493,26 @@ static int cs_etm__synth_instruction_sample(struct cs_etm_queue *etmq,
sample.stream_id = etmq->etm->instructions_id;
sample.period = period;
sample.cpu = tidq->packet->cpu;
- sample.flags = tidq->prev_packet->flags;
sample.cpumode = event->sample.header.misc;
- cs_etm__copy_insn(etmq, tidq->trace_chan_id, tidq->packet, &sample);
+ cs_etm__copy_insn(etmq, tidq->trace_chan_id, tidq->prev_packet, &sample);
+
+ /* Populate branch target information only when we encounter
+ * branch instruction, which is at the end of tidq->prev_packet.
+ */
+ if (addr == (tidq->prev_packet->end_addr - 4)) {
+ /* Update the perf_sample flags using the prev_packet
+ * since that is the queue we are synthesizing.
+ */
+ sample.flags = tidq->prev_packet->flags;
+
+ /* The last instruction of the previous queue would be a
+ * branch operation. Get the target of that branch by looking
+ * into the first executed instruction of the current packet
+ * queue.
+ */
+ sample.addr = cs_etm__first_executed_instr(tidq->packet);
+ }
if (etm->synth_opts.last_branch)
sample.branch_stack = tidq->last_branch;
@@ -1717,7 +1733,7 @@ static int cs_etm__sample(struct cs_etm_queue *etmq,
/* Get instructions remainder from previous packet */
instrs_prev = tidq->period_instructions;
- tidq->period_instructions += tidq->packet->instr_count;
+ tidq->period_instructions += tidq->prev_packet->instr_count;
/*
* Record a branch when the last instruction in
@@ -1797,8 +1813,11 @@ static int cs_etm__sample(struct cs_etm_queue *etmq,
* been executed, but PC has not advanced to next
* instruction)
*/
+ /* Get address from prev_packet since we are synthesizing
+ * that in cs_etm__synth_instruction_sample()
+ */
addr = cs_etm__instr_addr(etmq, trace_chan_id,
- tidq->packet, offset - 1);
+ tidq->prev_packet, offset - 1);
ret = cs_etm__synth_instruction_sample(
etmq, tidq, addr,
etm->instructions_sample_period);
@@ -1862,7 +1881,7 @@ static int cs_etm__flush(struct cs_etm_queue *etmq,
/* Handle start tracing packet */
if (tidq->prev_packet->sample_type == CS_ETM_EMPTY)
- goto swap_packet;
+ goto reset_last_br;
if (etmq->etm->synth_opts.last_branch &&
etmq->etm->synth_opts.instructions &&
@@ -1898,8 +1917,7 @@ static int cs_etm__flush(struct cs_etm_queue *etmq,
return err;
}
-swap_packet:
- cs_etm__packet_swap(etm, tidq);
+reset_last_br:
/* Reset last branches after flush the trace */
if (etm->synth_opts.last_branch)
--
2.34.1
next prev parent reply other threads:[~2024-04-04 18:09 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-04 18:07 [PATCH V2 0/2] Fix Coresight instruction synthesis logic Tanmay Jagdale
2024-04-04 18:07 ` Tanmay Jagdale [this message]
2024-04-04 18:07 ` [PATCH V2 2/2] perf: cs-etm: Store previous timestamp in packet queue Tanmay Jagdale
2024-04-25 18:54 ` [PATCH V2 0/2] Fix Coresight instruction synthesis logic Arnaldo Carvalho de Melo
2024-04-26 15:07 ` James Clark
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