From: Conor Dooley <conor@kernel.org>
To: Rajnesh Kanwal <rkanwal@rivosinc.com>
Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
linux-riscv@lists.infradead.org, adrian.hunter@intel.com,
alexander.shishkin@linux.intel.com, ajones@ventanamicro.com,
anup@brainfault.org, acme@kernel.org, atishp@rivosinc.com,
beeman@rivosinc.com, brauner@kernel.org, heiko@sntech.de,
irogers@google.com, mingo@redhat.com, james.clark@arm.com,
renyu.zj@linux.alibaba.com, jolsa@kernel.org,
jisheng.teoh@starfivetech.com, palmer@dabbelt.com,
tech-control-transfer-records@lists.riscv.org, will@kernel.org,
kaiwenxue1@gmail.com
Subject: Re: [PATCH RFC 3/6] riscv: perf: Add Control Transfer Records extension parsing
Date: Wed, 5 Jun 2024 19:06:40 +0100 [thread overview]
Message-ID: <20240605-thaw-giant-87eb299c43d0@spud> (raw)
In-Reply-To: <20240529185337.182722-4-rkanwal@rivosinc.com>
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On Wed, May 29, 2024 at 07:53:34PM +0100, Rajnesh Kanwal wrote:
> Adding CTR extension in ISA extension map to lookup for extension
> availability.
>
> Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
Same comment here about $subject.
You're also missing dt-bindings for the extension.
Thanks,
Conor.
> ---
> arch/riscv/include/asm/hwcap.h | 4 ++++
> arch/riscv/kernel/cpufeature.c | 2 ++
> 2 files changed, 6 insertions(+)
>
> diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> index b8cc459ee8a4..aff5ef398671 100644
> --- a/arch/riscv/include/asm/hwcap.h
> +++ b/arch/riscv/include/asm/hwcap.h
> @@ -86,6 +86,8 @@
> #define RISCV_ISA_EXT_SSCCFG 77
> #define RISCV_ISA_EXT_SMCDELEG 78
> #define RISCV_ISA_EXT_SMCNTRPMF 79
> +#define RISCV_ISA_EXT_SMCTR 80
> +#define RISCV_ISA_EXT_SSCTR 81
>
> #define RISCV_ISA_EXT_XLINUXENVCFG 127
>
> @@ -95,9 +97,11 @@
> #ifdef CONFIG_RISCV_M_MODE
> #define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SMAIA
> #define RISCV_ISA_EXT_SxCSRIND RISCV_ISA_EXT_SMCSRIND
> +#define RISCV_ISA_EXT_SxCTR RISCV_ISA_EXT_SMCTR
> #else
> #define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SSAIA
> #define RISCV_ISA_EXT_SxCSRIND RISCV_ISA_EXT_SSCSRIND
> +#define RISCV_ISA_EXT_SxCTR RISCV_ISA_EXT_SSCTR
> #endif
>
> #endif /* _ASM_RISCV_HWCAP_H */
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index d1fb6a8c5492..4334d822b2f2 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -298,6 +298,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
> __RISCV_ISA_EXT_DATA(zvkt, RISCV_ISA_EXT_ZVKT),
> __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA),
> __RISCV_ISA_EXT_DATA(smcdeleg, RISCV_ISA_EXT_SMCDELEG),
> + __RISCV_ISA_EXT_DATA(smctr, RISCV_ISA_EXT_SMCTR),
> __RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN),
> __RISCV_ISA_EXT_DATA(smcntrpmf, RISCV_ISA_EXT_SMCNTRPMF),
> __RISCV_ISA_EXT_DATA(smcsrind, RISCV_ISA_EXT_SMCSRIND),
> @@ -305,6 +306,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
> __RISCV_ISA_EXT_DATA(sscsrind, RISCV_ISA_EXT_SSCSRIND),
> __RISCV_ISA_EXT_DATA(ssccfg, RISCV_ISA_EXT_SSCCFG),
> __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
> + __RISCV_ISA_EXT_DATA(ssctr, RISCV_ISA_EXT_SSCTR),
> __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),
> __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL),
> __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT),
> --
> 2.34.1
>
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next prev parent reply other threads:[~2024-06-05 18:06 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-29 18:53 [PATCH RFC 0/6] riscv: perf: Add support for Control Transfer Records Ext Rajnesh Kanwal
2024-05-29 18:53 ` [PATCH RFC 1/6] perf: Increase the maximum number of samples to 256 Rajnesh Kanwal
2024-05-29 18:53 ` [PATCH RFC 2/6] riscv: perf: Add Control transfer records CSR definations Rajnesh Kanwal
2024-06-05 18:03 ` Conor Dooley
2024-06-10 11:09 ` Rajnesh Kanwal
2024-05-29 18:53 ` [PATCH RFC 3/6] riscv: perf: Add Control Transfer Records extension parsing Rajnesh Kanwal
2024-06-05 18:06 ` Conor Dooley [this message]
2024-05-29 18:53 ` [PATCH RFC 4/6] riscv: perf: Add infrastructure for Control Transfer Record Rajnesh Kanwal
2024-05-29 18:53 ` [PATCH RFC 5/6] riscv: perf: Add driver for Control Transfer Records Ext Rajnesh Kanwal
[not found] ` <CAPqJEFoJ4qz523nxccOD4VD=uufbwxfkR-5MDfzQFxGfiK+hrw@mail.gmail.com>
2024-08-27 10:01 ` Vincent Chen
2025-01-14 10:58 ` Rajnesh Kanwal
2025-01-14 17:55 ` Beeman Strong
2025-01-16 23:11 ` Rajnesh Kanwal
2024-09-05 21:52 ` Charlie Jenkins
2025-01-14 10:59 ` Rajnesh Kanwal
2024-05-29 18:53 ` [PATCH RFC 6/6] riscv: perf: Integrate CTR Ext support in riscv_pmu_dev driver Rajnesh Kanwal
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