From: Adrian Hunter <adrian.hunter@intel.com>
To: Peter Zijlstra <peterz@infradead.org>
Cc: Ingo Molnar <mingo@redhat.com>,
Thomas Gleixner <tglx@linutronix.de>,
Borislav Petkov <bp@alien8.de>,
Dave Hansen <dave.hansen@linux.intel.com>,
x86@kernel.org, H Peter Anvin <hpa@zytor.com>,
Mark Rutland <mark.rutland@arm.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Marco Cavenati <cavenati.marco@gmail.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Jiri Olsa <jolsa@kernel.org>, Namhyung Kim <namhyung@kernel.org>,
Ian Rogers <irogers@google.com>,
Kan Liang <kan.liang@linux.intel.com>,
linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org
Subject: [PATCH 2/7] perf/x86/intel/pt: Fix a topa_entry base address calculation
Date: Mon, 24 Jun 2024 23:10:56 +0300 [thread overview]
Message-ID: <20240624201101.60186-3-adrian.hunter@intel.com> (raw)
In-Reply-To: <20240624201101.60186-1-adrian.hunter@intel.com>
topa_entry->base is a bit-field. Bit-fields are not promoted to a 64-bit
type, even if the underlying type is 64-bit, and so, if necessary, must
be cast to a larger type when calculations are done.
Fix a topa_entry->base address calculation by adding a cast.
Without the cast, the address was limited to 36-bits i.e. 64GiB.
The address calculation is used on systems that do not support Multiple
Entry ToPA (only Broadwell), and affects physical addresses on or above
64GiB. Instead of writing to the correct address, the address comprising
the first 36 bits would be written to.
Intel PT snapshot and sampling modes are not affected.
Reported-by: Dave Hansen <dave.hansen@linux.intel.com>
Fixes: 52ca9ced3f70 ("perf/x86/intel/pt: Add Intel PT PMU driver")
Cc: stable@vger.kernel.org
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
---
arch/x86/events/intel/pt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/events/intel/pt.c b/arch/x86/events/intel/pt.c
index 14db6d9d318b..047a2cd5b3fe 100644
--- a/arch/x86/events/intel/pt.c
+++ b/arch/x86/events/intel/pt.c
@@ -878,7 +878,7 @@ static void pt_update_head(struct pt *pt)
*/
static void *pt_buffer_region(struct pt_buffer *buf)
{
- return phys_to_virt(TOPA_ENTRY(buf->cur, buf->cur_idx)->base << TOPA_SHIFT);
+ return phys_to_virt((phys_addr_t)TOPA_ENTRY(buf->cur, buf->cur_idx)->base << TOPA_SHIFT);
}
/**
--
2.34.1
next prev parent reply other threads:[~2024-06-24 20:11 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-24 20:10 [PATCH 0/7] perf: Intel PT and 64-bit AUX area size fixes Adrian Hunter
2024-06-24 20:10 ` [PATCH 1/7] perf/x86/intel/pt: Fix topa_entry base length Adrian Hunter
2024-06-24 20:10 ` Adrian Hunter [this message]
2024-06-24 20:10 ` [PATCH 3/7] perf/x86/intel/pt: Fix pt_topa_entry_for_page() address calculation Adrian Hunter
2024-06-24 20:10 ` [PATCH 4/7] perf: Fix perf_aux_size() for greater-than 32-bit size Adrian Hunter
2024-06-24 20:10 ` [PATCH 5/7] perf: Prevent passing zero nr_pages to rb_alloc_aux() Adrian Hunter
2024-06-24 20:11 ` [PATCH 6/7] perf: Fix default aux_watermark calculation Adrian Hunter
2024-06-24 20:11 ` [PATCH 7/7] perf: Make rb_alloc_aux() return an error immediately if nr_pages <= 0 Adrian Hunter
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