From: "Rob Herring (Arm)" <robh@kernel.org>
To: Russell King <linux@armlinux.org.uk>,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Namhyung Kim <namhyung@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Jiri Olsa <jolsa@kernel.org>, Ian Rogers <irogers@google.com>,
Adrian Hunter <adrian.hunter@intel.com>,
Will Deacon <will@kernel.org>, Marc Zyngier <maz@kernel.org>,
Oliver Upton <oliver.upton@linux.dev>,
James Morse <james.morse@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Zenghui Yu <yuzenghui@huawei.com>,
Catalin Marinas <catalin.marinas@arm.com>,
James Clark <james.clark@arm.com>
Cc: linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
kvmarm@lists.linux.dev
Subject: [PATCH v2 09/12] KVM: arm64: pmu: Use generated define for PMSELR_EL0.SEL access
Date: Wed, 26 Jun 2024 16:32:33 -0600 [thread overview]
Message-ID: <20240626-arm-pmu-3-9-icntr-v2-9-c9784b4f4065@kernel.org> (raw)
In-Reply-To: <20240626-arm-pmu-3-9-icntr-v2-0-c9784b4f4065@kernel.org>
ARMV8_PMU_COUNTER_MASK is really a mask for the PMSELR_EL0.SEL register
field. Make that clear by adding a standard sysreg definition for the
register, and using it instead.
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
---
arch/arm64/include/asm/sysreg.h | 1 -
arch/arm64/kvm/sys_regs.c | 10 +++++-----
arch/arm64/tools/sysreg | 5 +++++
include/linux/perf/arm_pmuv3.h | 1 -
4 files changed, 10 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index af3b206fa423..b0d6c33f9ecc 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -403,7 +403,6 @@
#define SYS_PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2)
#define SYS_PMOVSCLR_EL0 sys_reg(3, 3, 9, 12, 3)
#define SYS_PMSWINC_EL0 sys_reg(3, 3, 9, 12, 4)
-#define SYS_PMSELR_EL0 sys_reg(3, 3, 9, 12, 5)
#define SYS_PMCEID0_EL0 sys_reg(3, 3, 9, 12, 6)
#define SYS_PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7)
#define SYS_PMCCNTR_EL0 sys_reg(3, 3, 9, 13, 0)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 22b45a15d068..f8b5db48ea8a 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -880,7 +880,7 @@ static u64 reset_pmevtyper(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
static u64 reset_pmselr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
{
reset_unknown(vcpu, r);
- __vcpu_sys_reg(vcpu, r->reg) &= ARMV8_PMU_COUNTER_MASK;
+ __vcpu_sys_reg(vcpu, r->reg) &= PMSELR_EL0_SEL_MASK;
return __vcpu_sys_reg(vcpu, r->reg);
}
@@ -972,7 +972,7 @@ static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
else
/* return PMSELR.SEL field */
p->regval = __vcpu_sys_reg(vcpu, PMSELR_EL0)
- & ARMV8_PMU_COUNTER_MASK;
+ & PMSELR_EL0_SEL_MASK;
return true;
}
@@ -1040,8 +1040,8 @@ static bool access_pmu_evcntr(struct kvm_vcpu *vcpu,
if (pmu_access_event_counter_el0_disabled(vcpu))
return false;
- idx = __vcpu_sys_reg(vcpu, PMSELR_EL0)
- & ARMV8_PMU_COUNTER_MASK;
+ idx = SYS_FIELD_GET(PMSELR_EL0, SEL,
+ __vcpu_sys_reg(vcpu, PMSELR_EL0));
} else if (r->Op2 == 0) {
/* PMCCNTR_EL0 */
if (pmu_access_cycle_counter_el0_disabled(vcpu))
@@ -1091,7 +1091,7 @@ static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) {
/* PMXEVTYPER_EL0 */
- idx = __vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_PMU_COUNTER_MASK;
+ idx = SYS_FIELD_GET(PMSELR_EL0, SEL, __vcpu_sys_reg(vcpu, PMSELR_EL0));
reg = PMEVTYPER0_EL0 + idx;
} else if (r->CRn == 14 && (r->CRm & 12) == 12) {
idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index a4c1dd4741a4..231817a379b5 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -2153,6 +2153,11 @@ Field 4 P
Field 3:0 ALIGN
EndSysreg
+Sysreg PMSELR_EL0 3 3 9 12 5
+Res0 63:5
+Field 4:0 SEL
+EndSysreg
+
SysregFields CONTEXTIDR_ELx
Res0 63:32
Field 31:0 PROCID
diff --git a/include/linux/perf/arm_pmuv3.h b/include/linux/perf/arm_pmuv3.h
index eccbdd8eb98f..792b8e10b72a 100644
--- a/include/linux/perf/arm_pmuv3.h
+++ b/include/linux/perf/arm_pmuv3.h
@@ -8,7 +8,6 @@
#define ARMV8_PMU_MAX_GENERAL_COUNTERS 31
#define ARMV8_PMU_MAX_COUNTERS 32
-#define ARMV8_PMU_COUNTER_MASK (ARMV8_PMU_MAX_COUNTERS - 1)
/*
* Common architectural and microarchitectural event numbers.
--
2.43.0
next prev parent reply other threads:[~2024-06-26 22:32 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-26 22:32 [PATCH v2 00/12] arm64: Add support for Armv9.4 PMU fixed instruction counter Rob Herring (Arm)
2024-06-26 22:32 ` [PATCH v2 01/12] perf: arm_pmuv3: Avoid assigning fixed cycle counter with threshold Rob Herring (Arm)
2024-07-01 17:09 ` Mark Rutland
2024-06-26 22:32 ` [PATCH v2 02/12] perf: arm_pmuv3: Drop unnecessary IS_ENABLED(CONFIG_ARM64) check Rob Herring (Arm)
2024-07-01 17:11 ` Mark Rutland
2024-06-26 22:32 ` [PATCH v2 03/12] perf/arm: Move 32-bit PMU drivers to drivers/perf/ Rob Herring (Arm)
2024-06-26 22:32 ` [PATCH v2 04/12] perf: arm_v6/7_pmu: Drop non-DT probe support Rob Herring (Arm)
2024-06-26 22:32 ` [PATCH v2 05/12] perf: arm_pmuv3: Include asm/arm_pmuv3.h from linux/perf/arm_pmuv3.h Rob Herring (Arm)
2024-06-26 22:32 ` [PATCH v2 06/12] perf: arm_pmu: Remove event index to counter remapping Rob Herring (Arm)
2024-06-27 11:05 ` Marc Zyngier
2024-07-01 13:52 ` Will Deacon
2024-07-01 15:32 ` Mark Rutland
2024-07-01 15:49 ` Rob Herring
2024-07-02 16:19 ` Will Deacon
2024-07-01 17:06 ` Mark Rutland
2024-06-26 22:32 ` [PATCH v2 07/12] perf: arm_pmuv3: Prepare for more than 32 counters Rob Herring (Arm)
2024-06-26 22:32 ` [PATCH v2 08/12] KVM: arm64: pmu: Use arm_pmuv3.h register accessors Rob Herring (Arm)
2024-06-27 10:47 ` Marc Zyngier
2024-06-26 22:32 ` Rob Herring (Arm) [this message]
2024-06-27 10:47 ` [PATCH v2 09/12] KVM: arm64: pmu: Use generated define for PMSELR_EL0.SEL access Marc Zyngier
2024-06-26 22:32 ` [PATCH v2 10/12] arm64: perf/kvm: Use a common PMU cycle counter define Rob Herring (Arm)
2024-06-27 10:48 ` Marc Zyngier
2024-07-01 17:07 ` Mark Rutland
2024-06-26 22:32 ` [PATCH v2 11/12] KVM: arm64: Refine PMU defines for number of counters Rob Herring (Arm)
2024-06-27 10:54 ` Marc Zyngier
2024-06-26 22:32 ` [PATCH v2 12/12] perf: arm_pmuv3: Add support for Armv9.4 PMU instruction counter Rob Herring (Arm)
2024-07-01 17:20 ` Mark Rutland
2024-07-03 14:38 ` [PATCH v2 00/12] arm64: Add support for Armv9.4 PMU fixed " Will Deacon
2024-07-10 12:36 ` Will Deacon
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