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AJvYcCXK2vFNDizAWyUvZ9QlyGTFqIH6zXzubVkFljKjbwnrY8SPAgYHoyc1wa5nGlcpcOA6Md8QYnYnCR0RDipM/uEau+B7il68wkram7bAkybkZA== X-Gm-Message-State: AOJu0YwmNja4o0/SGHBbXqLb1l0igKF+hWLSM3IgmIG9ob8vCIUSIMDj i+HxRQbIOGFyEOVT8BJwVSUkoplnvf/2UQtwO9ll0Qos56uLWgUoQpfoWBz9gNs= X-Google-Smtp-Source: AGHT+IFngzTW8EHtTFvx7omE0v/qG3WhmjLl/7uA05MsoNd2N82RVXCmEyfoWoRu19pmQ31JPxhJiA== X-Received: by 2002:a05:6602:1605:b0:7f9:beb8:7952 with SMTP id ca18e2360f4ac-81711e19b10mr820491439f.13.1721321630783; Thu, 18 Jul 2024 09:53:50 -0700 (PDT) Received: from localhost ([140.82.166.162]) by smtp.gmail.com with ESMTPSA id 8926c6da1cb9f-4c210f24b6fsm1606088173.94.2024.07.18.09.53.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Jul 2024 09:53:50 -0700 (PDT) Date: Thu, 18 Jul 2024 11:53:49 -0500 From: Andrew Jones To: zhouquan@iscas.ac.cn Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-perf-users@vger.kernel.org, anup@brainfault.org, atishp@atishpatra.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, mark.rutland@arm.com, alexander.shishkin@linux.intel.com, jolsa@kernel.org Subject: Re: [PATCH 1/2] riscv: perf: add guest vs host distinction Message-ID: <20240718-e689be134be5b958b1eec65a@orel> References: <8e2d2f60fc30d64b6c69b38184a1b640c7b30003.1721271251.git.zhouquan@iscas.ac.cn> Precedence: bulk X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <8e2d2f60fc30d64b6c69b38184a1b640c7b30003.1721271251.git.zhouquan@iscas.ac.cn> On Thu, Jul 18, 2024 at 07:23:41PM GMT, zhouquan@iscas.ac.cn wrote: > From: Quan Zhou > > Introduce basic guest support in perf, enabling it to distinguish > between PMU interrupts in the host or guest, and collect > fundamental information. > > Signed-off-by: Quan Zhou > --- > arch/riscv/include/asm/perf_event.h | 7 ++++++ > arch/riscv/kernel/perf_callchain.c | 38 +++++++++++++++++++++++++++++ > 2 files changed, 45 insertions(+) > > diff --git a/arch/riscv/include/asm/perf_event.h b/arch/riscv/include/asm/perf_event.h > index 665bbc9b2f84..5866d028aee5 100644 > --- a/arch/riscv/include/asm/perf_event.h > +++ b/arch/riscv/include/asm/perf_event.h > @@ -8,13 +8,20 @@ > #ifndef _ASM_RISCV_PERF_EVENT_H > #define _ASM_RISCV_PERF_EVENT_H > > +#ifdef CONFIG_PERF_EVENTS > #include > #define perf_arch_bpf_user_pt_regs(regs) (struct user_regs_struct *)regs > > +extern unsigned long perf_instruction_pointer(struct pt_regs *regs); > +extern unsigned long perf_misc_flags(struct pt_regs *regs); > +#define perf_misc_flags(regs) perf_misc_flags(regs) > + > #define perf_arch_fetch_caller_regs(regs, __ip) { \ Arm has this outside the #ifdef CONFIG_PERF_EVENTS, but it doesn't look like it should be. > (regs)->epc = (__ip); \ > (regs)->s0 = (unsigned long) __builtin_frame_address(0); \ > (regs)->sp = current_stack_pointer; \ > (regs)->status = SR_PP; \ > } > +#endif > + > #endif /* _ASM_RISCV_PERF_EVENT_H */ > diff --git a/arch/riscv/kernel/perf_callchain.c b/arch/riscv/kernel/perf_callchain.c > index 3348a61de7d9..c673dc6d9bd2 100644 > --- a/arch/riscv/kernel/perf_callchain.c > +++ b/arch/riscv/kernel/perf_callchain.c > @@ -58,6 +58,11 @@ void perf_callchain_user(struct perf_callchain_entry_ctx *entry, > { > unsigned long fp = 0; > > + if (perf_guest_state()) { > + /* TODO: We don't support guest os callchain now */ > + return; > + } > + > fp = regs->s0; > perf_callchain_store(entry, regs->epc); > > @@ -74,5 +79,38 @@ static bool fill_callchain(void *entry, unsigned long pc) > void perf_callchain_kernel(struct perf_callchain_entry_ctx *entry, > struct pt_regs *regs) > { > + if (perf_guest_state()) { > + /* TODO: We don't support guest os callchain now */ > + return; > + } > + > walk_stackframe(NULL, regs, fill_callchain, entry); > } > + > +unsigned long perf_instruction_pointer(struct pt_regs *regs) > +{ > + if (perf_guest_state()) > + return perf_guest_get_ip(); > + > + return instruction_pointer(regs); > +} > + > +unsigned long perf_misc_flags(struct pt_regs *regs) > +{ > + unsigned int guest_state = perf_guest_state(); > + int misc = 0; Should use unsigned long for misc. > + > + if (guest_state) { > + if (guest_state & PERF_GUEST_USER) > + misc |= PERF_RECORD_MISC_GUEST_USER; > + else > + misc |= PERF_RECORD_MISC_GUEST_KERNEL; > + } else { > + if (user_mode(regs)) > + misc |= PERF_RECORD_MISC_USER; > + else > + misc |= PERF_RECORD_MISC_KERNEL; > + } > + > + return misc; > +} > -- > 2.34.1 > Thanks, drew