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Thu, 18 Jul 2024 08:45:28 GMT Received: from smtpav07.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id DDFDD2004D; Thu, 18 Jul 2024 08:45:25 +0000 (GMT) Received: from smtpav07.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id BD9F320043; Thu, 18 Jul 2024 08:45:22 +0000 (GMT) Received: from localhost.localdomain (unknown [9.43.69.1]) by smtpav07.fra02v.mail.ibm.com (Postfix) with ESMTP; Thu, 18 Jul 2024 08:45:22 +0000 (GMT) From: Athira Rajeev To: acme@kernel.org, jolsa@kernel.org, adrian.hunter@intel.com, irogers@google.com, namhyung@kernel.org, segher@kernel.crashing.org, christophe.leroy@csgroup.eu Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, akanksha@linux.ibm.com, maddy@linux.ibm.com, atrajeev@linux.vnet.ibm.com, kjain@linux.ibm.com, hbathini@linux.ibm.com, disgoel@linux.vnet.ibm.com Subject: [PATCH V8 10/15] tools/perf: Add more instructions for instruction tracking Date: Thu, 18 Jul 2024 14:13:53 +0530 Message-Id: <20240718084358.72242-11-atrajeev@linux.vnet.ibm.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20240718084358.72242-1-atrajeev@linux.vnet.ibm.com> References: <20240718084358.72242-1-atrajeev@linux.vnet.ibm.com> Precedence: bulk X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-TM-AS-GCONF: 00 X-Proofpoint-GUID: Tg6jpWx80NolWNEb17N9Ot43vS-cvzBe X-Proofpoint-ORIG-GUID: GYzzNvmcSdYGS_FjrifGg1HibPwsED0t X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-18_04,2024-07-17_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxlogscore=924 mlxscore=0 phishscore=0 suspectscore=0 bulkscore=0 clxscore=1015 spamscore=0 impostorscore=0 lowpriorityscore=0 malwarescore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2407180054 Add few more instructions and use opcode as search key to find if it is supported by the architecture. Added ones are: addi, addic, addic., addis, subfic and mulli Reviewed-and-tested-by: Kajol Jain Reviewed-by: Namhyung Kim Signed-off-by: Athira Rajeev --- tools/perf/arch/powerpc/annotate/instructions.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/tools/perf/arch/powerpc/annotate/instructions.c b/tools/perf/arch/powerpc/annotate/instructions.c index aa5ee09fa28f..aa25a336d8d0 100644 --- a/tools/perf/arch/powerpc/annotate/instructions.c +++ b/tools/perf/arch/powerpc/annotate/instructions.c @@ -172,6 +172,14 @@ static struct insn_offset arithmetic_ins_op_31[] = { { .name = "DIV_W_XO_FORM", .value = 491, }, }; +static struct insn_offset arithmetic_two_ops[] = { + { .name = "mulli", .value = 7, }, + { .name = "subfic", .value = 8, }, + { .name = "addic", .value = 12, }, + { .name = "addic.", .value = 13, }, + { .name = "addi", .value = 14, }, + { .name = "addis", .value = 15, }, +}; static int cmp_offset(const void *a, const void *b) { @@ -212,6 +220,12 @@ static struct ins_ops *check_ppc_insn(u32 raw_insn) if (PPC_21_30(raw_insn) == 444) return &arithmetic_ops; } + } else { + mem_insns_31_opcode.value = opcode; + ret = bsearch(&mem_insns_31_opcode, arithmetic_two_ops, ARRAY_SIZE(arithmetic_two_ops), + sizeof(arithmetic_two_ops[0]), cmp_offset); + if (ret != NULL) + return &arithmetic_ops; } return NULL; -- 2.43.0