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AJvYcCV7097epHbbbSqrUpwM7m6Ep5YSvJRnjvZmw4gJNM+TD8eKVvC4+AScLytaUgsumkPABRMnENJfICdg2vJfwcZ7bDDFgtcncMa4Ey4nwCAf5Q== X-Gm-Message-State: AOJu0Yz/5qaXaSGn384+21B/YU3dsDiZYF6pxoNjv5WmVlAfQOEtQXC7 aID7SKtir+X1gyLZjtQUvakJVeI3tnUTeVwTsKNmF4o15P6NRUd0nDfKuAJhBL0= X-Google-Smtp-Source: AGHT+IFkXu6WJB5QYfOAaZn9s1piO8yPCpYHKpBKZg8ljDLEmTZ0U7tZoZ2JfNjGtNrLvasw2PMYrQ== X-Received: by 2002:ad4:576d:0:b0:6b7:9b2c:98d3 with SMTP id 6a1803df08f44-6b79b2c9b20mr80138806d6.26.1721402473067; Fri, 19 Jul 2024 08:21:13 -0700 (PDT) Received: from localhost ([140.82.166.162]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-6b7acae194dsm8456146d6.107.2024.07.19.08.21.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Jul 2024 08:21:12 -0700 (PDT) Date: Fri, 19 Jul 2024 10:21:09 -0500 From: Andrew Jones To: Eric Lin Cc: peterz@infradead.org, mingo@redhat.com, acme@kernel.org, namhyung@kernel.org, alexander.shishkin@linux.intel.com, jolsa@kernel.org, irogers@google.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, peterlin@andestech.com, dminus@andestech.com, locus84@andestech.com, jisheng.teoh@starfivetech.com, inochiama@outlook.com, n.shubin@yadro.com, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Samuel Holland Subject: Re: [PATCH v2] perf arch events: Fix duplicate RISC-V SBI firmware event name Message-ID: <20240719-6219a417bc6fcf36ce67920f@orel> References: <20240719115018.27356-1-eric.lin@sifive.com> Precedence: bulk X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240719115018.27356-1-eric.lin@sifive.com> On Fri, Jul 19, 2024 at 07:50:18PM GMT, Eric Lin wrote: > Currently, the RISC-V firmware JSON file has duplicate event name > "FW_SFENCE_VMA_RECEIVED". According to the RISC-V SBI PMU extension[1], > the event name should be "FW_SFENCE_VMA_ASID_SENT". > > Before this patch: > $ perf list > > firmware: > fw_access_load > [Load access trap event. Unit: cpu] > fw_access_store > [Store access trap event. Unit: cpu] > .... > fw_set_timer > [Set timer event. Unit: cpu] > fw_sfence_vma_asid_received > [Received SFENCE.VMA with ASID request from other HART event. Unit: cpu] > fw_sfence_vma_received > [Sent SFENCE.VMA with ASID request to other HART event. Unit: cpu] > > After this patch: > $ perf list > > firmware: > fw_access_load > [Load access trap event. Unit: cpu] > fw_access_store > [Store access trap event. Unit: cpu] > ..... > fw_set_timer > [Set timer event. Unit: cpu] > fw_sfence_vma_asid_received > [Received SFENCE.VMA with ASID request from other HART event. Unit: cpu] > fw_sfence_vma_asid_sent > [Sent SFENCE.VMA with ASID request to other HART event. Unit: cpu] > fw_sfence_vma_received > [Received SFENCE.VMA request from other HART event. Unit: cpu] > > Link: https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/src/ext-pmu.adoc#event-firmware-events-type-15 [1] > Fixes: 8f0dcb4e7364 ("perf arch events: riscv sbi firmware std event files") > Fixes: c4f769d4093d ("perf vendor events riscv: add Sifive U74 JSON file") > Fixes: acbf6de674ef ("perf vendor events riscv: Add StarFive Dubhe-80 JSON file") > Fixes: 7340c6df49df ("perf vendor events riscv: add T-HEAD C9xx JSON file") > Fixes: f5102e31c209 ("riscv: andes: Support specifying symbolic firmware and hardware raw event") > Signed-off-by: Eric Lin > Reviewed-by: Samuel Holland > Reviewed-by: Nikita Shubin > --- > Changes since V1: > - Add "Fixes:" tag for every patch that copied firmware.json > --- > tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json | 2 +- > tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json | 2 +- > tools/perf/pmu-events/arch/riscv/sifive/u74/firmware.json | 2 +- > .../perf/pmu-events/arch/riscv/starfive/dubhe-80/firmware.json | 2 +- > .../perf/pmu-events/arch/riscv/thead/c900-legacy/firmware.json | 2 +- > 5 files changed, 5 insertions(+), 5 deletions(-) > > diff --git a/tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json b/tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json > index 9b4a032186a7..7149caec4f80 100644 > --- a/tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json > +++ b/tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json > @@ -36,7 +36,7 @@ > "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" > }, > { > - "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" > + "ArchStdEvent": "FW_SFENCE_VMA_ASID_SENT" > }, > { > "ArchStdEvent": "FW_SFENCE_VMA_ASID_RECEIVED" > diff --git a/tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json b/tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json > index a9939823b14b..0c9b9a2d2958 100644 > --- a/tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json > +++ b/tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json > @@ -74,7 +74,7 @@ > { > "PublicDescription": "Sent SFENCE.VMA with ASID request to other HART event", > "ConfigCode": "0x800000000000000c", > - "EventName": "FW_SFENCE_VMA_RECEIVED", > + "EventName": "FW_SFENCE_VMA_ASID_SENT", > "BriefDescription": "Sent SFENCE.VMA with ASID request to other HART event" > }, > { > diff --git a/tools/perf/pmu-events/arch/riscv/sifive/u74/firmware.json b/tools/perf/pmu-events/arch/riscv/sifive/u74/firmware.json > index 9b4a032186a7..7149caec4f80 100644 > --- a/tools/perf/pmu-events/arch/riscv/sifive/u74/firmware.json > +++ b/tools/perf/pmu-events/arch/riscv/sifive/u74/firmware.json > @@ -36,7 +36,7 @@ > "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" > }, > { > - "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" > + "ArchStdEvent": "FW_SFENCE_VMA_ASID_SENT" > }, > { > "ArchStdEvent": "FW_SFENCE_VMA_ASID_RECEIVED" > diff --git a/tools/perf/pmu-events/arch/riscv/starfive/dubhe-80/firmware.json b/tools/perf/pmu-events/arch/riscv/starfive/dubhe-80/firmware.json > index 9b4a032186a7..7149caec4f80 100644 > --- a/tools/perf/pmu-events/arch/riscv/starfive/dubhe-80/firmware.json > +++ b/tools/perf/pmu-events/arch/riscv/starfive/dubhe-80/firmware.json > @@ -36,7 +36,7 @@ > "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" > }, > { > - "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" > + "ArchStdEvent": "FW_SFENCE_VMA_ASID_SENT" > }, > { > "ArchStdEvent": "FW_SFENCE_VMA_ASID_RECEIVED" > diff --git a/tools/perf/pmu-events/arch/riscv/thead/c900-legacy/firmware.json b/tools/perf/pmu-events/arch/riscv/thead/c900-legacy/firmware.json > index 9b4a032186a7..7149caec4f80 100644 > --- a/tools/perf/pmu-events/arch/riscv/thead/c900-legacy/firmware.json > +++ b/tools/perf/pmu-events/arch/riscv/thead/c900-legacy/firmware.json > @@ -36,7 +36,7 @@ > "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" > }, > { > - "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" > + "ArchStdEvent": "FW_SFENCE_VMA_ASID_SENT" > }, > { > "ArchStdEvent": "FW_SFENCE_VMA_ASID_RECEIVED" > -- > 2.43.2 > Reviewed-by: Andrew Jones