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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CH2PEPF0000009D.mail.protection.outlook.com (10.167.244.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7918.13 via Frontend Transport; Fri, 13 Sep 2024 15:22:09 +0000 Received: from shatadru.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 13 Sep 2024 10:22:02 -0500 From: Dhananjay Ugwekar To: , , , , , , , , , , , , , , , , CC: , , , , , "Dhananjay Ugwekar" Subject: [PATCH v5 0/9] Add per-core RAPL energy counter support for AMD CPUs Date: Fri, 13 Sep 2024 15:21:40 +0000 Message-ID: <20240913152149.6317-1-Dhananjay.Ugwekar@amd.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000009D:EE_|SA1PR12MB6821:EE_ X-MS-Office365-Filtering-Correlation-Id: c0c66938-d91e-4a91-713a-08dcd407d57a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|1800799024|36860700013|82310400026|376014|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Sep 2024 15:22:09.0261 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c0c66938-d91e-4a91-713a-08dcd407d57a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000009D.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB6821 Currently the energy-cores event in the power PMU aggregates energy consumption data at a package level. On the other hand the core energy RAPL counter in AMD CPUs has a core scope (which means the energy consumption is recorded separately for each core). Earlier efforts to add the core event in the power PMU had failed [1], due to the difference in the scope of these two events. Hence, there is a need for a new core scope PMU. This patchset adds a new "power_per_core" PMU alongside the existing "power" PMU, which will be responsible for collecting the new "energy-per-core" event. Tested the package level and core level PMU counters with workloads pinned to different CPUs. Results with workload pinned to CPU 1 in Core 1 on an AMD Zen4 Genoa machine: $ perf stat -a --per-core -e power_per_core/energy-per-core/ -- sleep 1 Performance counter stats for 'system wide': S0-D0-C0 1 0.02 Joules power_per_core/energy-per-core/ S0-D0-C1 1 5.72 Joules power_per_core/energy-per-core/ S0-D0-C2 1 0.02 Joules power_per_core/energy-per-core/ S0-D0-C3 1 0.02 Joules power_per_core/energy-per-core/ S0-D0-C4 1 0.02 Joules power_per_core/energy-per-core/ S0-D0-C5 1 0.02 Joules power_per_core/energy-per-core/ S0-D0-C6 1 0.02 Joules power_per_core/energy-per-core/ S0-D0-C7 1 0.02 Joules power_per_core/energy-per-core/ S0-D0-C8 1 0.02 Joules power_per_core/energy-per-core/ S0-D0-C9 1 0.02 Joules power_per_core/energy-per-core/ S0-D0-C10 1 0.02 Joules power_per_core/energy-per-core/ v4 Link: https://lore.kernel.org/all/20240711102436.4432-1-Dhananjay.Ugwekar@amd.com/ v5 changes: * Rebase on top of Kan Liang's "PMU scope" patchset [2] * rapl_cntr_mask moved to rapl_pmus struct in patch 8 * Patch 1 from v4 is merged separately, so removed from this series * Add an extra argument "scope" in patch 5 to the init functions * Add an new patch 2, which removes the cpu_to_rapl_pmu() function Base: tip/perf/core(currently has just 1-5 patches from [2]) + patch 6 from [2] + diff [3] + patch 7 from [2] + revert [4] + apply [5] [1]: https://lore.kernel.org/lkml/3e766f0e-37d4-0f82-3868-31b14228868d@linux.intel.com/ [2]: https://lore.kernel.org/all/20240802151643.1691631-1-kan.liang@linux.intel.com/ [3]: https://lore.kernel.org/all/8c09633c-5bf2-48a2-91a6-a0af9b9f2e8c@linux.intel.com/ [4]: https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git/commit/?h=perf/core&id=8d72eba1cf8cecd76a2b4c1dd7673c2dc775f514 [5]: https://lore.kernel.org/all/20240910085504.204814-1-Dhananjay.Ugwekar@amd.com/ Dhananjay Ugwekar (8): perf/x86/rapl: Remove the cpu_to_rapl_pmu() function perf/x86/rapl: Rename rapl_pmu variables perf/x86/rapl: Make rapl_model struct global perf/x86/rapl: Add arguments to the cleanup and init functions perf/x86/rapl: Modify the generic variable names to *_pkg* perf/x86/rapl: Remove the global variable rapl_msrs perf/x86/rapl: Move the cntr_mask to rapl_pmus struct perf/x86/rapl: Add per-core energy counter support for AMD CPUs K Prateek Nayak (1): x86/topology: Introduce topology_logical_core_id() Documentation/arch/x86/topology.rst | 4 + arch/x86/events/rapl.c | 406 ++++++++++++++++---------- arch/x86/include/asm/processor.h | 1 + arch/x86/include/asm/topology.h | 1 + arch/x86/kernel/cpu/debugfs.c | 1 + arch/x86/kernel/cpu/topology_common.c | 1 + 6 files changed, 266 insertions(+), 148 deletions(-) -- 2.34.1