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client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BL6PEPF0001AB4F.mail.protection.outlook.com (10.167.242.73) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8356.11 via Frontend Transport; Wed, 15 Jan 2025 15:50:08 +0000 Received: from BLR-L-RBANGORI.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Wed, 15 Jan 2025 09:50:03 -0600 From: Ravi Bangoria To: , CC: , , , , , , , , , , , , Subject: [UNTESTED][PATCH] perf/x86: Fix limit_period() for 'freq mode events' Date: Wed, 15 Jan 2025 15:49:49 +0000 Message-ID: <20250115154949.3147-1-ravi.bangoria@amd.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB4F:EE_|PH7PR12MB9202:EE_ X-MS-Office365-Filtering-Correlation-Id: 5b2e73f0-dd79-48e4-d8f6-08dd357c49f7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|82310400026|36860700013|1800799024; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Jan 2025 15:50:08.9049 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5b2e73f0-dd79-48e4-d8f6-08dd357c49f7 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB4F.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB9202 For the freq mode event ... event->attr.sample_period contains sampling freq, not the sample period. So, use actual sample period (event->hw.sample_period) while calling limit_period(). Kernel dynamically adjusts event sample period after every sample to meet the desire sampling freq. For this, kernel starts with sample period = 1 and gradually increase it. Instead of simply returning error, start calibrating freq with the minimum sample period provided by limit_period(). Similarly, value provided along with ioctl(PERF_EVENT_IOC_PERIOD) contains new freq not the sample period. Avoid calling limit_period() for freq mode event in the ioctl() code path. Signed-off-by: Ravi Bangoria --- UNTESTED: limit_period() is mostly defined by Intel PMUs and I don't have any of those test machines. arch/x86/events/core.c | 23 +++++++++++++++++++---- 1 file changed, 19 insertions(+), 4 deletions(-) diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index c75c482d4c52..924aa35676d3 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -629,10 +629,22 @@ int x86_pmu_hw_config(struct perf_event *event) event->hw.config |= x86_pmu_get_event_config(event); if (event->attr.sample_period && x86_pmu.limit_period) { - s64 left = event->attr.sample_period; - x86_pmu.limit_period(event, &left); - if (left > event->attr.sample_period) - return -EINVAL; + if (event->attr.freq) { + s64 left = event->hw.sample_period; + + x86_pmu.limit_period(event, &left); + if (left != event->hw.sample_period) { + event->hw.sample_period = left; + event->hw.last_period = left; + local64_set(&event->hw.period_left, left); + } + } else { + s64 left = event->attr.sample_period; + + x86_pmu.limit_period(event, &left); + if (left > event->attr.sample_period) + return -EINVAL; + } } /* sample_regs_user never support XMM registers */ @@ -2648,6 +2660,9 @@ static int x86_pmu_check_period(struct perf_event *event, u64 value) if (x86_pmu.check_period && x86_pmu.check_period(event, value)) return -EINVAL; + if (event->attr.freq) + return 0; + if (value && x86_pmu.limit_period) { s64 left = value; x86_pmu.limit_period(event, &left); -- 2.34.1