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Wed, 05 Feb 2025 23:23:41 -0800 (PST) From: Atish Patra Date: Wed, 05 Feb 2025 23:23:21 -0800 Subject: [PATCH v4 16/21] RISC-V: perf: Use config2/vendor table for event to counter mapping Precedence: bulk X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20250205-counter_delegation-v4-16-835cfa88e3b1@rivosinc.com> References: <20250205-counter_delegation-v4-0-835cfa88e3b1@rivosinc.com> In-Reply-To: <20250205-counter_delegation-v4-0-835cfa88e3b1@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Anup Patel , Atish Patra , Will Deacon , Mark Rutland , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , weilin.wang@intel.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Conor Dooley , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, Atish Patra X-Mailer: b4 0.15-dev-13183 The counter restriction specified in the json file is passed to the drivers via config2 paarameter in perf attributes. This allows any platform vendor to define their custom mapping between event and hpmcounters without any rules defined in the ISA. For legacy events, the platform vendor may define the mapping in the driver in the vendor event table. The fixed cycle and instruction counters are fixed (0 and 2 respectively) by the ISA and maps to the legacy events. The platform vendor must specify this in the driver if intended to be used while profiling. Otherwise, they can just specify the alternate hpmcounters that may monitor and/or sample the cycle/instruction counts. Signed-off-by: Atish Patra --- drivers/perf/riscv_pmu_dev.c | 79 ++++++++++++++++++++++++++++++++++-------- include/linux/perf/riscv_pmu.h | 2 ++ 2 files changed, 67 insertions(+), 14 deletions(-) diff --git a/drivers/perf/riscv_pmu_dev.c b/drivers/perf/riscv_pmu_dev.c index 219f65eb167c..bbf5bcff51fc 100644 --- a/drivers/perf/riscv_pmu_dev.c +++ b/drivers/perf/riscv_pmu_dev.c @@ -76,6 +76,7 @@ static ssize_t __maybe_unused rvpmu_format_show(struct device *dev, struct devic RVPMU_ATTR_ENTRY(_name, rvpmu_format_show, (char *)_config) PMU_FORMAT_ATTR(firmware, "config:62-63"); +PMU_FORMAT_ATTR(counterid_mask, "config2:0-31"); static bool sbi_v2_available; static DEFINE_STATIC_KEY_FALSE(sbi_pmu_snapshot_available); @@ -112,6 +113,7 @@ static const struct attribute_group *riscv_sbi_pmu_attr_groups[] = { static struct attribute *riscv_cdeleg_pmu_formats_attr[] = { RVPMU_FORMAT_ATTR_ENTRY(event, RVPMU_CDELEG_PMU_FORMAT_ATTR), &format_attr_firmware.attr, + &format_attr_counterid_mask.attr, NULL, }; @@ -1383,24 +1385,77 @@ static int rvpmu_deleg_find_ctrs(void) return num_hw_ctr; } +/* + * The json file must correctly specify counter 0 or counter 2 is available + * in the counter lists for cycle/instret events. Otherwise, the drivers have + * no way to figure out if a fixed counter must be used and pick a programmable + * counter if available. + */ static int get_deleg_fixed_hw_idx(struct cpu_hw_events *cpuc, struct perf_event *event) { - return -EINVAL; + struct hw_perf_event *hwc = &event->hw; + bool guest_events = event->attr.config1 & RISCV_PMU_CONFIG1_GUEST_EVENTS; + + if (guest_events) { + if (hwc->event_base == SBI_PMU_HW_CPU_CYCLES) + return 0; + if (hwc->event_base == SBI_PMU_HW_INSTRUCTIONS) + return 2; + else + return -EINVAL; + } + + if (!event->attr.config2) + return -EINVAL; + + if (event->attr.config2 & RISCV_PMU_CYCLE_FIXED_CTR_MASK) + return 0; /* CY counter */ + else if (event->attr.config2 & RISCV_PMU_INSTRUCTION_FIXED_CTR_MASK) + return 2; /* IR counter */ + else + return -EINVAL; } static int get_deleg_next_hpm_hw_idx(struct cpu_hw_events *cpuc, struct perf_event *event) { - unsigned long hw_ctr_mask = 0; + u32 hw_ctr_mask = 0, temp_mask = 0; + u32 type = event->attr.type; + u64 config = event->attr.config; + int ret; - /* - * TODO: Treat every hpmcounter can monitor every event for now. - * The event to counter mapping should come from the json file. - * The mapping should also tell if sampling is supported or not. - */ + /* Select only available hpmcounters */ + hw_ctr_mask = cmask & (~0x7) & ~(cpuc->used_hw_ctrs[0]); + + switch (type) { + case PERF_TYPE_HARDWARE: + temp_mask = current_pmu_hw_event_map[config].counter_mask; + break; + case PERF_TYPE_HW_CACHE: + ret = cdeleg_pmu_event_find_cache(config, NULL, &temp_mask); + if (ret) + return ret; + break; + case PERF_TYPE_RAW: + /* + * Mask off the counters that can't monitor this event (specified via json) + * The counter mask for this event is set in config2 via the property 'Counter' + * in the json file or manual configuration of config2. If the config2 is not set, + * it is assumed all the available hpmcounters can monitor this event. + * Note: This assumption may fail for virtualization use case where they hypervisor + * (e.g. KVM) virtualizes the counter. Any event to counter mapping provided by the + * guest is meaningless from a hypervisor perspective. Thus, the hypervisor doesn't + * set config2 when creating kernel counter and relies default host mapping. + */ + if (event->attr.config2) + temp_mask = event->attr.config2; + break; + default: + break; + } + + if (temp_mask) + hw_ctr_mask &= temp_mask; - /* Select only hpmcounters */ - hw_ctr_mask = cmask & (~0x7); - hw_ctr_mask &= ~(cpuc->used_hw_ctrs[0]); return __ffs(hw_ctr_mask); } @@ -1429,10 +1484,6 @@ static int rvpmu_deleg_ctr_get_idx(struct perf_event *event) u64 priv_filter; int idx; - /* - * TODO: We should not rely on SBI Perf encoding to check if the event - * is a fixed one or not. - */ if (!is_sampling_event(event)) { idx = get_deleg_fixed_hw_idx(cpuc, event); if (idx == 0 || idx == 2) { diff --git a/include/linux/perf/riscv_pmu.h b/include/linux/perf/riscv_pmu.h index 9e2758c32e8b..e58f83811988 100644 --- a/include/linux/perf/riscv_pmu.h +++ b/include/linux/perf/riscv_pmu.h @@ -30,6 +30,8 @@ #define RISCV_PMU_CONFIG1_GUEST_EVENTS 0x1 #define RISCV_PMU_DELEG_RAW_EVENT_MASK GENMASK_ULL(55, 0) +#define RISCV_PMU_CYCLE_FIXED_CTR_MASK 0x01 +#define RISCV_PMU_INSTRUCTION_FIXED_CTR_MASK 0x04 #define HW_OP_UNSUPPORTED 0xFFFF #define CACHE_OP_UNSUPPORTED 0xFFFF -- 2.43.0