From: Nick Chan <towinchenmi@gmail.com>
To: Will Deacon <will@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Catalin Marinas <catalin.marinas@arm.com>
Cc: Marc Zyngier <maz@kernel.org>,
linux-arm-kernel@lists.infradead.org,
linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org,
asahi@lists.linux.dev, linux-kernel@vger.kernel.org,
Nick Chan <towinchenmi@gmail.com>
Subject: [PATCH 03/10] drivers/perf: apple_m1: Support a per-implementation number of counters
Date: Wed, 12 Feb 2025 00:07:24 +0800 [thread overview]
Message-ID: <20250212-apple-cpmu-v1-3-f8c7f2ac1743@gmail.com> (raw)
In-Reply-To: <20250212-apple-cpmu-v1-0-f8c7f2ac1743@gmail.com>
Support a per-implementation number of counters to allow adding support
for implementations with less counters.
Signed-off-by: Nick Chan <towinchenmi@gmail.com>
---
drivers/perf/apple_m1_cpu_pmu.c | 31 ++++++++++++++++++++-----------
1 file changed, 20 insertions(+), 11 deletions(-)
diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pmu.c
index 1bf7ce5c09846c699d66bdfcca129f418a9dad9e..ae91848bcd828be197fc21bb2195f3e2460edc65 100644
--- a/drivers/perf/apple_m1_cpu_pmu.c
+++ b/drivers/perf/apple_m1_cpu_pmu.c
@@ -19,6 +19,7 @@
#include <asm/perf_event.h>
#define M1_PMU_NR_COUNTERS 10
+#define APPLE_PMU_MAX_NR_COUNTERS 10
#define M1_PMU_CFG_EVENT GENMASK(7, 0)
@@ -431,7 +432,7 @@ static irqreturn_t m1_pmu_handle_irq(struct arm_pmu *cpu_pmu)
regs = get_irq_regs();
- for_each_set_bit(idx, cpu_pmu->cntr_mask, M1_PMU_NR_COUNTERS) {
+ for_each_set_bit(idx, cpu_pmu->cntr_mask, APPLE_PMU_MAX_NR_COUNTERS) {
struct perf_event *event = cpuc->events[idx];
struct perf_sample_data data;
@@ -479,7 +480,7 @@ static int apple_pmu_get_event_idx(struct pmu_hw_events *cpuc,
* counting on the PMU at any given time, and by placing the
* most constraining events first.
*/
- for_each_set_bit(idx, &affinity, M1_PMU_NR_COUNTERS) {
+ for_each_set_bit(idx, &affinity, APPLE_PMU_MAX_NR_COUNTERS) {
if (!test_and_set_bit(idx, cpuc->used_mask))
return idx;
}
@@ -554,13 +555,13 @@ static int m2_pmu_map_event(struct perf_event *event)
return apple_pmu_map_event_63(event, &m1_pmu_perf_map);
}
-static void m1_pmu_reset(void *info)
+static void apple_pmu_reset_common(void *info, u32 counters)
{
int i;
__m1_pmu_set_mode(PMCR0_IMODE_OFF);
- for (i = 0; i < M1_PMU_NR_COUNTERS; i++) {
+ for (i = 0; i < counters; i++) {
m1_pmu_disable_counter(i);
m1_pmu_disable_counter_interrupt(i);
m1_pmu_write_hw_counter(0, i);
@@ -569,6 +570,11 @@ static void m1_pmu_reset(void *info)
isb();
}
+static void m1_pmu_reset(void *info)
+{
+ apple_pmu_reset_common(info, M1_PMU_NR_COUNTERS);
+}
+
static int m1_pmu_set_event_filter(struct hw_perf_event *event,
struct perf_event_attr *attr)
{
@@ -588,7 +594,7 @@ static int m1_pmu_set_event_filter(struct hw_perf_event *event,
return 0;
}
-static int apple_pmu_init_common(struct arm_pmu *cpu_pmu, u32 flags)
+static int apple_pmu_init_common(struct arm_pmu *cpu_pmu, u32 flags, u32 counters)
{
cpu_pmu->handle_irq = m1_pmu_handle_irq;
cpu_pmu->enable = m1_pmu_enable_event;
@@ -598,10 +604,9 @@ static int apple_pmu_init_common(struct arm_pmu *cpu_pmu, u32 flags)
cpu_pmu->clear_event_idx = m1_pmu_clear_event_idx;
cpu_pmu->start = m1_pmu_start;
cpu_pmu->stop = m1_pmu_stop;
- cpu_pmu->reset = m1_pmu_reset;
cpu_pmu->set_event_filter = m1_pmu_set_event_filter;
- bitmap_set(cpu_pmu->cntr_mask, 0, M1_PMU_NR_COUNTERS);
+ bitmap_set(cpu_pmu->cntr_mask, 0, counters);
cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = &m1_pmu_events_attr_group;
cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = &m1_pmu_format_attr_group;
return 0;
@@ -613,7 +618,8 @@ static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu)
cpu_pmu->name = "apple_icestorm_pmu";
cpu_pmu->get_event_idx = m1_pmu_get_event_idx;
cpu_pmu->map_event = m1_pmu_map_event;
- return apple_pmu_init_common(cpu_pmu, ARMPMU_EVT_47BIT);
+ cpu_pmu->reset = m1_pmu_reset;
+ return apple_pmu_init_common(cpu_pmu, ARMPMU_EVT_47BIT, M1_PMU_NR_COUNTERS);
}
static int m1_pmu_fire_init(struct arm_pmu *cpu_pmu)
@@ -621,7 +627,8 @@ static int m1_pmu_fire_init(struct arm_pmu *cpu_pmu)
cpu_pmu->name = "apple_firestorm_pmu";
cpu_pmu->get_event_idx = m1_pmu_get_event_idx;
cpu_pmu->map_event = m1_pmu_map_event;
- return apple_pmu_init_common(cpu_pmu, ARMPMU_EVT_47BIT);
+ cpu_pmu->reset = m1_pmu_reset;
+ return apple_pmu_init_common(cpu_pmu, ARMPMU_EVT_47BIT, M1_PMU_NR_COUNTERS);
}
static int m2_pmu_avalanche_init(struct arm_pmu *cpu_pmu)
@@ -629,7 +636,8 @@ static int m2_pmu_avalanche_init(struct arm_pmu *cpu_pmu)
cpu_pmu->name = "apple_avalanche_pmu";
cpu_pmu->get_event_idx = m1_pmu_get_event_idx;
cpu_pmu->map_event = m2_pmu_map_event;
- return apple_pmu_init_common(cpu_pmu, ARMPMU_EVT_63BIT);
+ cpu_pmu->reset = m1_pmu_reset;
+ return apple_pmu_init_common(cpu_pmu, ARMPMU_EVT_63BIT, M1_PMU_NR_COUNTERS);
}
static int m2_pmu_blizzard_init(struct arm_pmu *cpu_pmu)
@@ -637,7 +645,8 @@ static int m2_pmu_blizzard_init(struct arm_pmu *cpu_pmu)
cpu_pmu->name = "apple_blizzard_pmu";
cpu_pmu->get_event_idx = m1_pmu_get_event_idx;
cpu_pmu->map_event = m2_pmu_map_event;
- return apple_pmu_init_common(cpu_pmu, ARMPMU_EVT_63BIT);
+ cpu_pmu->reset = m1_pmu_reset;
+ return apple_pmu_init_common(cpu_pmu, ARMPMU_EVT_63BIT, M1_PMU_NR_COUNTERS);
}
static const struct of_device_id m1_pmu_of_device_ids[] = {
--
2.48.1
next prev parent reply other threads:[~2025-02-11 16:08 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-11 16:07 [PATCH 00/10] drivers/perf: apple_m1: Add Apple A7-A11, T2 SoC support Nick Chan
2025-02-11 16:07 ` [PATCH 01/10] dt-bindings: arm: pmu: Add Apple A7-A11 SoC CPU PMU compatibles Nick Chan
2025-02-11 16:07 ` [PATCH 02/10] drivers/perf: apple_m1: Support per-implementation event tables Nick Chan
2025-02-12 1:46 ` Nick Chan
2025-02-11 16:07 ` Nick Chan [this message]
2025-02-11 16:07 ` [PATCH 04/10] drivers/perf: apple_m1: Support configuring counters for 32-bit EL0 Nick Chan
2025-02-11 16:07 ` [PATCH 05/10] drivers/perf: apple_m1: Support per-implementation PMU start Nick Chan
2025-02-11 16:07 ` [PATCH 06/10] drivers/perf: apple_m1: Add Apple A7 support Nick Chan
2025-02-11 16:07 ` [PATCH 07/10] drivers/perf: apple_m1: Add Apple A8/A8X support Nick Chan
2025-02-11 16:07 ` [PATCH 08/10] drivers/perf: apple_m1: Add A9/A9X support Nick Chan
2025-02-11 16:07 ` [PATCH 09/10] drivers/perf: apple_m1: Add Apple A10/A10X/T2 Support Nick Chan
2025-02-11 16:07 ` [PATCH 10/10] drivers/perf: apple_m1: Add Apple A11 Support Nick Chan
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