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Date: Fri, 23 May 2025 00:25:06 +0100 Message-Id: <20250523-b4-ctr_upstream_v3-v3-0-ad355304ba1c@rivosinc.com> Precedence: bulk X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIAFKyL2gC/6tWKk4tykwtVrJSqFYqSi3LLM7MzwNyjHUUlJIzE vPSU3UzU4B8JSMDI1MDE0Mz3SQT3eSSovjSguKSotTE3PgyY10jA5M0kySDJHMTC0MloMaCotS 0zAqwodGxtbUA8z9ytWQAAAA= X-Change-ID: 20250416-b4-ctr_upstream_v3-204f4b0b7481 To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Atish Kumar Patra , Anup Patel , Will Deacon , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Beeman Strong Cc: linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Palmer Dabbelt , Conor Dooley , devicetree@vger.kernel.org, Rajnesh Kanwal X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1747956375; l=5043; i=rkanwal@rivosinc.com; s=20250522; h=from:subject:message-id; bh=Xt+9J5CINKC67/Xf9FTS32L9c6buwlWjqj4FpG7qyTQ=; b=voXbtY/BvjLgr1Qk+pdKoA/M9txQ+Uo8IZDt/nVzmOvCl9hu8Lrpi2vmzjOnKtVTdNeWIIAkS zuOwbL5C0z1CmtoSdzyA2XjmkKpBnAPcjkCDaiTFuIC9KKpMB7oMk1P X-Developer-Key: i=rkanwal@rivosinc.com; a=ed25519; pk=aw8nvncslGKHEmTBTJqvkP/4tj6pijL8fwRRym/GuS8= This series enables Control Transfer Records extension support on riscv architecture. This extension is similar to Arch LBR in x86 and BRBE in ARM. The Extension has been ratified and latest release can be found here [0] CTR extension depends on both the implementation of S-mode and Sscsrind extension v1.0.0 [1]. CTR access ctrsource, ctrtartget and ctrdata CSRs using sscsrind extension. The series is based on Smcdeleg/Ssccfg counter delegation extension [2] patches [3]. CTR itself doesn't depend on counter delegation support. This rebase is basically to include the Smcsrind patches. The last patch is in the perf tool to allow processing 256 entries. Without this perf seems to consider that sample as corrupted and discards it. Here is the link to a quick guide [4] to setup and run a basic perf demo on Linux to use CTR Ext. Qemu patches are merged upstream: https://lore.kernel.org/qemu-devel/20250205-b4-ctr_upstream_v6-v6-0-439d8e06c8ef@rivosinc.com/ Opensbi patch is merged upstream: https://lore.kernel.org/opensbi/20250307124451.122828-1-rkanwal@rivosinc.com/ Linux kernel patches can be found here: https://github.com/rajnesh-kanwal/linux/tree/b4/ctr_upstream_v3 [0]: https://github.com/riscv/riscv-control-transfer-records/releases/tag/v1.0 [1]: https://github.com/riscvarchive/riscv-indirect-csr-access/releases/tag/v1.0.0 [2]: https://github.com/riscvarchive/riscv-smcdeleg-ssccfg/releases/tag/v1.0.0 [3]: https://lore.kernel.org/lkml/20250114-counter_delegation-v2-0-8ba74cdb851b@rivosinc.com/ [4]: https://github.com/rajnesh-kanwal/linux/wiki/Running-CTR-basic-demo-on-QEMU-RISC%E2%80%90V-Virt-machine To: Peter Zijlstra To: Ingo Molnar To: Arnaldo Carvalho de Melo To: Namhyung Kim To: Mark Rutland To: Alexander Shishkin To: Jiri Olsa To: Ian Rogers To: Adrian Hunter To: Liang, Kan To: Paul Walmsley To: Palmer Dabbelt To: Albert Ou To: Alexandre Ghiti To: Atish Kumar Patra To: Anup Patel To: Will Deacon To: Rob Herring To: Krzysztof Kozlowski To: Conor Dooley To: Beeman Strong Cc: linux-perf-users@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-riscv@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org Cc: Palmer Dabbelt Cc: Conor Dooley Cc: devicetree@vger.kernel.org Signed-off-by: Rajnesh Kanwal --- Changelog: v3: - Added missing To/Cc, especially devicetree@vger.kernel.org - Changed the commit description to better describe the need of perf tool change that increases max sample size processing capacity of remove_loops function. - Minor fixes found while doing a virtualization PoC. - Added the missing commit and repository information to dt-bindings, indicating where the extension was ratified. v2 - Added context save/restore support for tasks using CTR feature. - https://lore.kernel.org/lkml/20250116230955.867152-1-rkanwal@rivosinc.com/ v1: - https://lore.kernel.org/lkml/20240529185337.182722-1-rkanwal@rivosinc.com/ --- --- Rajnesh Kanwal (7): perf: Increase the maximum number of branches remove_loops() can process. riscv: pmu: Add Control transfer records CSR definations. riscv: Add Control Transfer Records extension parsing riscv: pmu: Add infrastructure for Control Transfer Record riscv: pmu: Add driver for Control Transfer Records Ext. riscv: pmu: Integrate CTR Ext support in riscv_pmu_dev driver dt-bindings: riscv: add Sxctr ISA extension description .../devicetree/bindings/riscv/extensions.yaml | 28 + MAINTAINERS | 1 + arch/riscv/include/asm/csr.h | 83 +++ arch/riscv/include/asm/hwcap.h | 4 + arch/riscv/kernel/cpufeature.c | 2 + drivers/perf/Kconfig | 11 + drivers/perf/Makefile | 1 + drivers/perf/riscv_ctr.c | 612 +++++++++++++++++++++ drivers/perf/riscv_pmu_common.c | 25 +- drivers/perf/riscv_pmu_dev.c | 82 +++ drivers/perf/riscv_pmu_legacy.c | 2 + include/linux/perf/riscv_pmu.h | 55 ++ tools/perf/util/machine.c | 21 +- 13 files changed, 918 insertions(+), 9 deletions(-) --- base-commit: e0200e37637e573cd68f522ecd550be87e304c6c change-id: 20250416-b4-ctr_upstream_v3-204f4b0b7481 Best regards, -- Rajnesh Kanwal