From: Colton Lewis <coltonlewis@google.com>
To: kvm@vger.kernel.org
Cc: Paolo Bonzini <pbonzini@redhat.com>,
Jonathan Corbet <corbet@lwn.net>,
Russell King <linux@armlinux.org.uk>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>, Marc Zyngier <maz@kernel.org>,
Oliver Upton <oliver.upton@linux.dev>,
Joey Gouly <joey.gouly@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Zenghui Yu <yuzenghui@huawei.com>,
Mark Rutland <mark.rutland@arm.com>,
Shuah Khan <shuah@kernel.org>,
linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev,
linux-perf-users@vger.kernel.org,
linux-kselftest@vger.kernel.org,
Colton Lewis <coltonlewis@google.com>
Subject: [PATCH 15/17] KVM: arm64: Inject recorded guest interrupts
Date: Mon, 2 Jun 2025 19:27:00 +0000 [thread overview]
Message-ID: <20250602192702.2125115-16-coltonlewis@google.com> (raw)
In-Reply-To: <20250602192702.2125115-1-coltonlewis@google.com>
When we re-enter the VM after handling a PMU interrupt, calculate
whether it was any of the guest counters that overflowed and inject an
interrupt into the guest if so.
Signed-off-by: Colton Lewis <coltonlewis@google.com>
---
arch/arm64/include/asm/kvm_host.h | 3 ++-
arch/arm64/kvm/pmu-emul.c | 4 ++--
arch/arm64/kvm/pmu-part.c | 22 +++++++++++++++++++++-
arch/arm64/kvm/pmu.c | 7 ++++++-
4 files changed, 31 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
index 955359f20161..0af8cc4c340f 100644
--- a/arch/arm64/include/asm/kvm_host.h
+++ b/arch/arm64/include/asm/kvm_host.h
@@ -1714,9 +1714,10 @@ bool kvm_vcpu_pmu_is_partitioned(struct kvm_vcpu *vcpu);
struct kvm_pmu_events *kvm_get_pmu_events(void);
void kvm_vcpu_pmu_restore_guest(struct kvm_vcpu *vcpu);
void kvm_vcpu_pmu_restore_host(struct kvm_vcpu *vcpu);
-bool kvm_pmu_overflow_status(struct kvm_vcpu *vcpu);
+bool kvm_pmu_emul_overflow_status(struct kvm_vcpu *vcpu);
void kvm_pmu_load(struct kvm_vcpu *vcpu);
void kvm_pmu_put(struct kvm_vcpu *vcpu);
+bool kvm_pmu_part_overflow_status(struct kvm_vcpu *vcpu);
/*
* Updates the vcpu's view of the pmu events for this cpu.
diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c
index ff86c66e1b48..0ffabada1dad 100644
--- a/arch/arm64/kvm/pmu-emul.c
+++ b/arch/arm64/kvm/pmu-emul.c
@@ -320,7 +320,7 @@ void kvm_pmu_reprogram_counter_mask(struct kvm_vcpu *vcpu, u64 val)
* counter where the values of the global enable control, PMOVSSET_EL0[n], and
* PMINTENSET_EL1[n] are all 1.
*/
-bool kvm_pmu_overflow_status(struct kvm_vcpu *vcpu)
+bool kvm_pmu_emul_overflow_status(struct kvm_vcpu *vcpu)
{
u64 reg = __vcpu_sys_reg(vcpu, PMOVSSET_EL0);
@@ -457,7 +457,7 @@ static void kvm_pmu_perf_overflow(struct perf_event *perf_event,
kvm_pmu_counter_increment(vcpu, BIT(idx + 1),
ARMV8_PMUV3_PERFCTR_CHAIN);
- if (kvm_pmu_overflow_status(vcpu)) {
+ if (kvm_pmu_emul_overflow_status(vcpu)) {
kvm_make_request(KVM_REQ_IRQ_PENDING, vcpu);
if (!in_nmi())
diff --git a/arch/arm64/kvm/pmu-part.c b/arch/arm64/kvm/pmu-part.c
index 0e1a2235e992..1d85e7ce76c8 100644
--- a/arch/arm64/kvm/pmu-part.c
+++ b/arch/arm64/kvm/pmu-part.c
@@ -252,7 +252,7 @@ void kvm_pmu_load(struct kvm_vcpu *vcpu)
write_pmcr(val);
/*
- * Loading these registers is tricky because of
+ * Loading these registers is more intricate because of
* 1. Applying only the bits for guest counters (indicated by mask)
* 2. Setting and clearing are different registers
*/
@@ -336,3 +336,23 @@ void kvm_pmu_handle_guest_irq(u64 govf)
__vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= govf;
}
+
+/**
+ * kvm_pmu_part_overflow_status() - Determine if any guest counters have overflowed
+ * @vcpu: Ponter to struct kvm_vcpu
+ *
+ * Determine if any guest counters have overflowed and therefore an
+ * IRQ needs to be injected into the guest.
+ *
+ * Return: True if there was an overflow, false otherwise
+ */
+bool kvm_pmu_part_overflow_status(struct kvm_vcpu *vcpu)
+{
+ struct arm_pmu *pmu = vcpu->kvm->arch.arm_pmu;
+ u64 mask = kvm_pmu_guest_counter_mask(pmu);
+ u64 pmovs = __vcpu_sys_reg(vcpu, PMOVSSET_EL0);
+ u64 pmint = read_pmintenset();
+ u64 pmcr = read_pmcr();
+
+ return (pmcr & ARMV8_PMU_PMCR_E) && (mask & pmovs & pmint);
+}
diff --git a/arch/arm64/kvm/pmu.c b/arch/arm64/kvm/pmu.c
index 2dcfac3ea9c6..6c3151dec25a 100644
--- a/arch/arm64/kvm/pmu.c
+++ b/arch/arm64/kvm/pmu.c
@@ -425,7 +425,11 @@ static void kvm_pmu_update_state(struct kvm_vcpu *vcpu)
struct kvm_pmu *pmu = &vcpu->arch.pmu;
bool overflow;
- overflow = kvm_pmu_overflow_status(vcpu);
+ if (kvm_vcpu_pmu_is_partitioned(vcpu))
+ overflow = kvm_pmu_part_overflow_status(vcpu);
+ else
+ overflow = kvm_pmu_emul_overflow_status(vcpu);
+
if (pmu->irq_level == overflow)
return;
@@ -694,6 +698,7 @@ int kvm_arm_pmu_v3_set_attr(struct kvm_vcpu *vcpu, struct kvm_device_attr *attr)
return -EBUSY;
kvm_debug("Set kvm ARM PMU irq: %d\n", irq);
+
vcpu->arch.pmu.irq_num = irq;
return 0;
}
--
2.49.0.1204.g71687c7c1d-goog
next prev parent reply other threads:[~2025-06-02 19:29 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-02 19:26 [PATCH 00/17] ARM64 PMU Partitioning Colton Lewis
2025-06-02 19:26 ` [PATCH 01/17] arm64: cpufeature: Add cpucap for HPMN0 Colton Lewis
2025-06-02 22:15 ` Oliver Upton
2025-06-03 20:50 ` Colton Lewis
2025-06-02 19:26 ` [PATCH 02/17] arm64: Generate sign macro for sysreg Enums Colton Lewis
2025-06-02 19:26 ` [PATCH 03/17] arm64: cpufeature: Add cpucap for PMICNTR Colton Lewis
2025-06-02 19:26 ` [PATCH 04/17] KVM: arm64: Cleanup PMU includes Colton Lewis
2025-06-02 21:42 ` Sean Christopherson
2025-06-03 20:48 ` Colton Lewis
2025-06-02 19:26 ` [PATCH 05/17] KVM: arm64: Reorganize PMU functions Colton Lewis
2025-06-02 19:26 ` [PATCH 06/17] KVM: arm64: Introduce method to partition the PMU Colton Lewis
2025-06-02 22:28 ` Oliver Upton
2025-06-03 21:32 ` Colton Lewis
2025-06-03 22:02 ` Oliver Upton
2025-06-04 20:10 ` Colton Lewis
2025-06-04 20:57 ` Oliver Upton
2025-06-02 19:26 ` [PATCH 07/17] perf: arm_pmuv3: Generalize counter bitmasks Colton Lewis
2025-06-02 19:26 ` [PATCH 08/17] perf: arm_pmuv3: Keep out of guest counter partition Colton Lewis
2025-06-02 19:26 ` [PATCH 09/17] KVM: arm64: Set up FGT for Partitioned PMU Colton Lewis
2025-06-02 19:26 ` [PATCH 10/17] KVM: arm64: Writethrough trapped PMEVTYPER register Colton Lewis
2025-06-03 22:22 ` Oliver Upton
2025-06-04 20:10 ` Colton Lewis
2025-06-02 19:26 ` [PATCH 11/17] KVM: arm64: Use physical PMSELR for PMXEVTYPER if partitioned Colton Lewis
2025-06-02 19:26 ` [PATCH 12/17] KVM: arm64: Writethrough trapped PMOVS register Colton Lewis
2025-06-02 19:26 ` [PATCH 13/17] KVM: arm64: Context switch Partitioned PMU guest registers Colton Lewis
2025-06-02 19:26 ` [PATCH 14/17] perf: pmuv3: Handle IRQs for Partitioned PMU guest counters Colton Lewis
2025-06-02 19:27 ` Colton Lewis [this message]
2025-06-02 19:27 ` [PATCH 16/17] KVM: arm64: Add ioctl to partition the PMU when supported Colton Lewis
2025-06-02 22:40 ` Oliver Upton
2025-06-03 21:46 ` Colton Lewis
2025-06-04 20:12 ` Colton Lewis
2025-06-02 19:27 ` [PATCH 17/17] KVM: arm64: selftests: Add test case for partitioned PMU Colton Lewis
2025-06-03 22:43 ` [PATCH 00/17] ARM64 PMU Partitioning Oliver Upton
2025-06-04 20:10 ` Colton Lewis
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