From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C5F6F25B682 for ; Wed, 11 Jun 2025 09:03:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749632631; cv=none; b=VLp3erlVF62CcOlZ8xrYxjfBYl14wVwKpiJAFBV6xfXqgK7d49aSHFJXZvKKp4WoF6U/kLJv7dSN5pzvDLNsY/fhdJQK1s1FSZ/yO7S1ziog4rN+3MKrBjuWY7Qs0ZySooFJNz4/oSwwbaSa1CehZt05nPZhnx18+SMoyQJ3vXM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749632631; c=relaxed/simple; bh=gcNHWEPxMAhCNg3T9OJ5l7Jvp/kYYtNEvD+YnKVYfhc=; h=Date:From:To:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=LXg5YbxBR1XC8/u4t4fZ6Eq473rgWvNBWoT9/F3Xor7VTMSVzoHo+lIV/itkPv2vvqqHWUWsIvHCpb94YB/EzgwJ4g0nsOscJklsNr6hP4I/zxKvbGVODHp6CM4/e4jvgL9EmadQeZPYv/ao2zfxvALWuVzCVjYJuRGrQzRPmnM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 789E41688; Wed, 11 Jun 2025 02:03:22 -0700 (PDT) Received: from localhost (e132581.arm.com [10.1.196.87]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A70C93F59E; Wed, 11 Jun 2025 02:03:41 -0700 (PDT) Date: Wed, 11 Jun 2025 10:03:37 +0100 From: Leo Yan To: Will Deacon , Mark Rutland , James Clark , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org Subject: Re: [PATCH v2] perf: arm_spe: Relax period restriction Message-ID: <20250611090337.GS8020@e132581.arm.com> References: <20250528132501.129586-1-leo.yan@arm.com> Precedence: bulk X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250528132501.129586-1-leo.yan@arm.com> On Wed, May 28, 2025 at 02:25:01PM +0100, Leo Yan wrote: > The minimum interval specified the PMSIDR_EL1.Interval field is a > hardware recommendation. However, this value is set by hardware designer > before the production. It may not accurately reflects actual hardware > limitations, and tools currently have no way to test shorter periods. > > This change relaxes the limitation by allowing any non-zero periods. > This gives chance for experimenting smaller periods. > > The downside is that small periods may increase the risk of AUX ring > buffer overruns. When an overrun occurs, the perf core layer will > trigger an irq work to disable the event and wake up the tool in user > space to read the trace data. After the tool finishes reading, it will > re-enable the AUX event. > > Signed-off-by: Leo Yan Gentle ping. thanks! > --- > > Changes from v1: > - Shifted bits with FIELD_PREP(). > - Removed warning log which is not quite useful. (James Clark) > > drivers/perf/arm_spe_pmu.c | 10 +++++++--- > 1 file changed, 7 insertions(+), 3 deletions(-) > > diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c > index 3efed8839a4e..e40e5daa838d 100644 > --- a/drivers/perf/arm_spe_pmu.c > +++ b/drivers/perf/arm_spe_pmu.c > @@ -308,12 +308,16 @@ static u64 arm_spe_event_to_pmscr(struct perf_event *event) > > static void arm_spe_event_sanitise_period(struct perf_event *event) > { > - struct arm_spe_pmu *spe_pmu = to_spe_pmu(event->pmu); > u64 period = event->hw.sample_period; > u64 max_period = PMSIRR_EL1_INTERVAL_MASK; > > - if (period < spe_pmu->min_period) > - period = spe_pmu->min_period; > + /* > + * As per the Arm ARM (DDI 0487 L.a), section D24.7.12 PMSIRR_EL1, > + * Sampling Interval Reload Register, the INTERVAL field (bits [31:8]) > + * states: "Software must set this to a nonzero value." > + */ > + if (period < FIELD_PREP(PMSIRR_EL1_INTERVAL_MASK, 1)) > + period = FIELD_PREP(PMSIRR_EL1_INTERVAL_MASK, 1); > else if (period > max_period) > period = max_period; > else > -- > 2.34.1 >