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From: Nick Chan <towinchenmi@gmail.com>
To: Will Deacon <will@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	 Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	 Conor Dooley <conor+dt@kernel.org>,
	 Catalin Marinas <catalin.marinas@arm.com>,
	Janne Grunau <j@jannau.net>,
	 Alyssa Rosenzweig <alyssa@rosenzweig.io>,
	Neal Gompa <neal@gompa.dev>,  Sven Peter <sven@kernel.org>
Cc: Marc Zyngier <maz@kernel.org>,
	linux-arm-kernel@lists.infradead.org,
	 linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org,
	 asahi@lists.linux.dev, linux-kernel@vger.kernel.org,
	 Nick Chan <towinchenmi@gmail.com>
Subject: [PATCH RESEND v7 04/21] drivers/perf: apple_m1: Support a per-implementation number of counters
Date: Mon, 16 Jun 2025 09:31:53 +0800	[thread overview]
Message-ID: <20250616-apple-cpmu-v7-4-df2778a44d5c@gmail.com> (raw)
In-Reply-To: <20250616-apple-cpmu-v7-0-df2778a44d5c@gmail.com>

Support a per-implementation number of counters to allow adding support
for implementations with less counters.

Signed-off-by: Nick Chan <towinchenmi@gmail.com>
---
 drivers/perf/apple_m1_cpu_pmu.c | 31 ++++++++++++++++++++-----------
 1 file changed, 20 insertions(+), 11 deletions(-)

diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pmu.c
index c19a433ee6478876e4cf6667d7a85a193b6cb069..35a34eca403384c4908c2bba2f8186ea854d63bf 100644
--- a/drivers/perf/apple_m1_cpu_pmu.c
+++ b/drivers/perf/apple_m1_cpu_pmu.c
@@ -20,6 +20,7 @@
 #include <asm/perf_event.h>
 
 #define M1_PMU_NR_COUNTERS		10
+#define APPLE_PMU_MAX_NR_COUNTERS	10
 
 #define M1_PMU_CFG_EVENT		GENMASK(7, 0)
 
@@ -459,7 +460,7 @@ static irqreturn_t m1_pmu_handle_irq(struct arm_pmu *cpu_pmu)
 
 	regs = get_irq_regs();
 
-	for_each_set_bit(idx, cpu_pmu->cntr_mask, M1_PMU_NR_COUNTERS) {
+	for_each_set_bit(idx, cpu_pmu->cntr_mask, APPLE_PMU_MAX_NR_COUNTERS) {
 		struct perf_event *event = cpuc->events[idx];
 		struct perf_sample_data data;
 
@@ -507,7 +508,7 @@ static int apple_pmu_get_event_idx(struct pmu_hw_events *cpuc,
 	 * counting on the PMU at any given time, and by placing the
 	 * most constraining events first.
 	 */
-	for_each_set_bit(idx, &affinity, M1_PMU_NR_COUNTERS) {
+	for_each_set_bit(idx, &affinity, APPLE_PMU_MAX_NR_COUNTERS) {
 		if (!test_and_set_bit(idx, cpuc->used_mask))
 			return idx;
 	}
@@ -602,13 +603,13 @@ static void m1_pmu_init_pmceid(struct arm_pmu *pmu)
 	}
 }
 
-static void m1_pmu_reset(void *info)
+static void apple_pmu_reset(void *info, u32 counters)
 {
 	int i;
 
 	__m1_pmu_set_mode(PMCR0_IMODE_OFF);
 
-	for (i = 0; i < M1_PMU_NR_COUNTERS; i++) {
+	for (i = 0; i < counters; i++) {
 		m1_pmu_disable_counter(i);
 		m1_pmu_disable_counter_interrupt(i);
 		m1_pmu_write_hw_counter(0, i);
@@ -617,6 +618,11 @@ static void m1_pmu_reset(void *info)
 	isb();
 }
 
+static void m1_pmu_reset(void *info)
+{
+	apple_pmu_reset(info, M1_PMU_NR_COUNTERS);
+}
+
 static int m1_pmu_set_event_filter(struct hw_perf_event *event,
 				   struct perf_event_attr *attr)
 {
@@ -640,7 +646,7 @@ static int m1_pmu_set_event_filter(struct hw_perf_event *event,
 	return 0;
 }
 
-static int apple_pmu_init(struct arm_pmu *cpu_pmu)
+static int apple_pmu_init(struct arm_pmu *cpu_pmu, u32 counters)
 {
 	cpu_pmu->handle_irq	  = m1_pmu_handle_irq;
 	cpu_pmu->enable		  = m1_pmu_enable_event;
@@ -650,7 +656,6 @@ static int apple_pmu_init(struct arm_pmu *cpu_pmu)
 	cpu_pmu->clear_event_idx  = m1_pmu_clear_event_idx;
 	cpu_pmu->start		  = m1_pmu_start;
 	cpu_pmu->stop		  = m1_pmu_stop;
-	cpu_pmu->reset		  = m1_pmu_reset;
 	cpu_pmu->set_event_filter = m1_pmu_set_event_filter;
 
 	if (is_hyp_mode_available()) {
@@ -658,7 +663,7 @@ static int apple_pmu_init(struct arm_pmu *cpu_pmu)
 		m1_pmu_init_pmceid(cpu_pmu);
 	}
 
-	bitmap_set(cpu_pmu->cntr_mask, 0, M1_PMU_NR_COUNTERS);
+	bitmap_set(cpu_pmu->cntr_mask, 0, counters);
 	cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = &m1_pmu_events_attr_group;
 	cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = &m1_pmu_format_attr_group;
 	return 0;
@@ -670,7 +675,8 @@ static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu)
 	cpu_pmu->name = "apple_icestorm_pmu";
 	cpu_pmu->get_event_idx	  = m1_pmu_get_event_idx;
 	cpu_pmu->map_event	  = m1_pmu_map_event;
-	return apple_pmu_init(cpu_pmu);
+	cpu_pmu->reset		  = m1_pmu_reset;
+	return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS);
 }
 
 static int m1_pmu_fire_init(struct arm_pmu *cpu_pmu)
@@ -678,7 +684,8 @@ static int m1_pmu_fire_init(struct arm_pmu *cpu_pmu)
 	cpu_pmu->name = "apple_firestorm_pmu";
 	cpu_pmu->get_event_idx	  = m1_pmu_get_event_idx;
 	cpu_pmu->map_event	  = m1_pmu_map_event;
-	return apple_pmu_init(cpu_pmu);
+	cpu_pmu->reset		  = m1_pmu_reset;
+	return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS);
 }
 
 static int m2_pmu_avalanche_init(struct arm_pmu *cpu_pmu)
@@ -686,7 +693,8 @@ static int m2_pmu_avalanche_init(struct arm_pmu *cpu_pmu)
 	cpu_pmu->name = "apple_avalanche_pmu";
 	cpu_pmu->get_event_idx	  = m1_pmu_get_event_idx;
 	cpu_pmu->map_event	  = m2_pmu_map_event;
-	return apple_pmu_init(cpu_pmu);
+	cpu_pmu->reset		  = m1_pmu_reset;
+	return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS);
 }
 
 static int m2_pmu_blizzard_init(struct arm_pmu *cpu_pmu)
@@ -694,7 +702,8 @@ static int m2_pmu_blizzard_init(struct arm_pmu *cpu_pmu)
 	cpu_pmu->name = "apple_blizzard_pmu";
 	cpu_pmu->get_event_idx	  = m1_pmu_get_event_idx;
 	cpu_pmu->map_event	  = m2_pmu_map_event;
-	return apple_pmu_init(cpu_pmu);
+	cpu_pmu->reset		  = m1_pmu_reset;
+	return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS);
 }
 
 static const struct of_device_id m1_pmu_of_device_ids[] = {

-- 
2.49.0


  parent reply	other threads:[~2025-06-16  1:32 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-16  1:31 [PATCH RESEND v7 00/21] drivers/perf: apple_m1: Add Apple A7-A11, T2 SoC support Nick Chan
2025-06-16  1:31 ` [PATCH RESEND v7 01/21] dt-bindings: arm: pmu: Add Apple A7-A11 SoC CPU PMU compatibles Nick Chan
2025-06-16  1:31 ` [PATCH RESEND v7 02/21] drivers/perf: apple_m1: Only init PMUv3 remap when EL2 is available Nick Chan
2025-07-14 15:11   ` Will Deacon
2025-07-14 15:37     ` Nick Chan
2025-07-17 15:16       ` Will Deacon
2025-06-16  1:31 ` [PATCH RESEND v7 03/21] drivers/perf: apple_m1: Support per-implementation event tables Nick Chan
2025-06-16  1:31 ` Nick Chan [this message]
2025-06-16  1:31 ` [PATCH RESEND v7 05/21] drivers/perf: apple_m1: Support configuring counters for 32-bit EL0 Nick Chan
2025-07-14 15:12   ` Will Deacon
2025-06-16  1:31 ` [PATCH RESEND v7 06/21] drivers/perf: apple_m1: Support per-implementation PMU startup Nick Chan
2025-06-16  1:31 ` [PATCH RESEND v7 07/21] drivers/perf: apple_m1: Support per-implementation event attr group Nick Chan
2025-06-16  1:31 ` [PATCH RESEND v7 08/21] drivers/perf: apple_m1: Add Apple A7 support Nick Chan
2025-06-16  1:31 ` [PATCH RESEND v7 09/21] drivers/perf: apple_m1: Add Apple A8/A8X support Nick Chan
2025-06-16  1:31 ` [PATCH RESEND v7 10/21] drivers/perf: apple_m1: Add A9/A9X support Nick Chan
2025-06-16  1:32 ` [PATCH RESEND v7 11/21] drivers/perf: apple_m1: Add Apple A10/A10X/T2 Support Nick Chan
2025-06-16  1:32 ` [PATCH RESEND v7 12/21] drivers/perf: apple_m1: Add Apple A11 Support Nick Chan
2025-06-16  1:32 ` [PATCH RESEND v7 13/21] arm64: dts: apple: s5l8960x: Add CPU PMU nodes Nick Chan
2025-06-16  1:32 ` [PATCH RESEND v7 14/21] arm64: dts: apple: t7000: " Nick Chan
2025-06-16  1:32 ` [PATCH RESEND v7 15/21] arm64: dts: apple: t7001: " Nick Chan
2025-06-16  1:32 ` [PATCH RESEND v7 16/21] arm64: dts: apple: s800-0-3: " Nick Chan
2025-06-16  1:32 ` [PATCH RESEND v7 17/21] arm64: dts: apple: s8001: " Nick Chan
2025-06-16  1:32 ` [PATCH RESEND v7 18/21] arm64: dts: apple: t8010: " Nick Chan
2025-06-16  1:32 ` [PATCH RESEND v7 19/21] arm64: dts: apple: t8011: " Nick Chan
2025-06-16  1:32 ` [PATCH RESEND v7 20/21] arm64: dts: apple: t8012: " Nick Chan
2025-06-16  1:32 ` [PATCH RESEND v7 21/21] arm64: dts: apple: t8015: " Nick Chan
2025-06-16  9:36 ` [PATCH RESEND v7 00/21] drivers/perf: apple_m1: Add Apple A7-A11, T2 SoC support Ian Rogers
2025-06-16 10:29   ` Will Deacon
2025-06-16 10:44     ` Ian Rogers
2025-06-17 14:16       ` Will Deacon
2025-06-17 16:28         ` Ian Rogers
2025-06-17 16:47         ` Marc Zyngier
2025-06-17 16:53           ` Ian Rogers
2025-06-16 10:35   ` Nick Chan
2025-07-14 15:12 ` Will Deacon
2025-07-14 15:59   ` Nick Chan
2025-07-17 15:05     ` Mark Rutland
2025-07-17 17:00       ` Nick Chan
2025-07-18 15:01         ` Mark Rutland
2025-07-18 20:45           ` Nick Chan

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