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From: Dapeng Mi <dapeng1.mi@linux.intel.com>
To: Peter Zijlstra <peterz@infradead.org>,
	Ingo Molnar <mingo@redhat.com>,
	Arnaldo Carvalho de Melo <acme@kernel.org>,
	Namhyung Kim <namhyung@kernel.org>,
	Ian Rogers <irogers@google.com>,
	Adrian Hunter <adrian.hunter@intel.com>,
	Alexander Shishkin <alexander.shishkin@linux.intel.com>,
	Kan Liang <kan.liang@linux.intel.com>,
	Andi Kleen <ak@linux.intel.com>,
	Eranian Stephane <eranian@google.com>
Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
	Dapeng Mi <dapeng1.mi@intel.com>,
	Dapeng Mi <dapeng1.mi@linux.intel.com>
Subject: [Patch v4 08/13] perf/x86/intel: Update dyn_constranit base on PEBS event precise level
Date: Fri, 20 Jun 2025 10:39:04 +0000	[thread overview]
Message-ID: <20250620103909.1586595-9-dapeng1.mi@linux.intel.com> (raw)
In-Reply-To: <20250620103909.1586595-1-dapeng1.mi@linux.intel.com>

arch-PEBS provides CPUIDs to enumerate which counters support PEBS
sampling and precise distribution PEBS sampling. Thus PEBS constraints
should be dynamically configured base on these counter and precise
distribution bitmap instead of defining them statically.

Update event dyn_constraint base on PEBS event precise level.

Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
---
 arch/x86/events/intel/core.c | 11 +++++++++++
 arch/x86/events/intel/ds.c   |  1 +
 2 files changed, 12 insertions(+)

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 5e6ef9f3a077..00b41c693d13 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -4255,6 +4255,8 @@ static int intel_pmu_hw_config(struct perf_event *event)
 	}
 
 	if (event->attr.precise_ip) {
+		struct arch_pebs_cap pebs_cap = hybrid(event->pmu, arch_pebs_cap);
+
 		if ((event->attr.config & INTEL_ARCH_EVENT_MASK) == INTEL_FIXED_VLBR_EVENT)
 			return -EINVAL;
 
@@ -4268,6 +4270,15 @@ static int intel_pmu_hw_config(struct perf_event *event)
 		}
 		if (x86_pmu.pebs_aliases)
 			x86_pmu.pebs_aliases(event);
+
+		if (x86_pmu.arch_pebs) {
+			u64 cntr_mask = hybrid(event->pmu, intel_ctrl) &
+						~GLOBAL_CTRL_EN_PERF_METRICS;
+			u64 pebs_mask = event->attr.precise_ip >= 3 ?
+						pebs_cap.pdists : pebs_cap.counters;
+			if (cntr_mask != pebs_mask)
+				event->hw.dyn_constraint &= pebs_mask;
+		}
 	}
 
 	if (needs_branch_stack(event)) {
diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
index 72b925b8c482..30915338b929 100644
--- a/arch/x86/events/intel/ds.c
+++ b/arch/x86/events/intel/ds.c
@@ -2987,6 +2987,7 @@ static void __init intel_arch_pebs_init(void)
 	x86_pmu.pebs_buffer_size = PEBS_BUFFER_SIZE;
 	x86_pmu.drain_pebs = intel_pmu_drain_arch_pebs;
 	x86_pmu.pebs_capable = ~0ULL;
+	x86_pmu.flags |= PMU_FL_PEBS_ALL;
 
 	x86_pmu.pebs_enable = __intel_pmu_pebs_enable;
 	x86_pmu.pebs_disable = __intel_pmu_pebs_disable;
-- 
2.43.0


  parent reply	other threads:[~2025-06-20  7:29 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-20 10:38 [Patch v4 00/13] arch-PEBS enabling for Intel platforms Dapeng Mi
2025-06-20 10:38 ` [Patch v4 01/13] perf/x86/intel: Replace x86_pmu.drain_pebs calling with static call Dapeng Mi
2025-06-20 10:38 ` [Patch v4 02/13] perf/x86/intel: Correct large PEBS flag check Dapeng Mi
2025-06-20 10:38 ` [Patch v4 03/13] perf/x86/intel: Initialize architectural PEBS Dapeng Mi
2025-06-20 10:39 ` [Patch v4 04/13] perf/x86/intel/ds: Factor out PEBS record processing code to functions Dapeng Mi
2025-06-20 10:39 ` [Patch v4 05/13] perf/x86/intel/ds: Factor out PEBS group " Dapeng Mi
2025-06-20 10:39 ` [Patch v4 06/13] perf/x86/intel: Process arch-PEBS records or record fragments Dapeng Mi
2025-06-20 10:39 ` [Patch v4 07/13] perf/x86/intel: Allocate arch-PEBS buffer and initialize PEBS_BASE MSR Dapeng Mi
2025-06-21  9:20   ` Peter Zijlstra
2025-06-23  1:17     ` Mi, Dapeng
2025-06-23  7:28       ` Peter Zijlstra
2025-06-23  8:41         ` Mi, Dapeng
2025-06-20 10:39 ` Dapeng Mi [this message]
2025-06-20 10:39 ` [Patch v4 09/13] perf/x86/intel: Setup PEBS data configuration and enable legacy groups Dapeng Mi
2025-06-21  9:27   ` Peter Zijlstra
2025-06-23  1:20     ` Mi, Dapeng
2025-06-21  9:34   ` Peter Zijlstra
2025-06-23  1:38     ` Mi, Dapeng
2025-06-21  9:36   ` Peter Zijlstra
2025-06-23  1:39     ` Mi, Dapeng
2025-06-21  9:41   ` Peter Zijlstra
2025-06-23  1:55     ` Mi, Dapeng
2025-06-21  9:43   ` Peter Zijlstra
2025-06-23  1:55     ` Mi, Dapeng
2025-06-20 10:39 ` [Patch v4 10/13] perf/x86/intel: Add counter group support for arch-PEBS Dapeng Mi
2025-06-20 10:39 ` [Patch v4 11/13] perf/x86: Support to sample SSP register Dapeng Mi
2025-06-20 10:39 ` [Patch v4 12/13] perf/x86/intel: Support to sample SSP register for arch-PEBS Dapeng Mi
2025-06-20 10:39 ` [Patch v4 13/13] perf tools: x86: Support to show SSP register Dapeng Mi

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