From: Dapeng Mi <dapeng1.mi@linux.intel.com>
To: Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Namhyung Kim <namhyung@kernel.org>,
Ian Rogers <irogers@google.com>,
Adrian Hunter <adrian.hunter@intel.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Kan Liang <kan.liang@linux.intel.com>,
Andi Kleen <ak@linux.intel.com>,
Eranian Stephane <eranian@google.com>
Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
Dapeng Mi <dapeng1.mi@intel.com>,
Dapeng Mi <dapeng1.mi@linux.intel.com>
Subject: [Patch v5 02/10] perf/x86/intel: Correct large PEBS flag check
Date: Mon, 23 Jun 2025 22:35:37 +0000 [thread overview]
Message-ID: <20250623223546.112465-3-dapeng1.mi@linux.intel.com> (raw)
In-Reply-To: <20250623223546.112465-1-dapeng1.mi@linux.intel.com>
current large PEBS flag check only checks if sample_regs_user contains
unsupported GPRs but doesn't check if sample_regs_intr contains
unsupported GPRs.
Of course, currently PEBS HW supports to sample all perf supported GPRs,
the missed check doesn't cause real issue. But it won't be true any more
after the subsequent patches support to sample SSP register. SSP
sampling is not supported by adaptive PEBS HW and it would be supported
until arch-PEBS HW. So correct this issue.
Fixes: a47ba4d77e12 ("perf/x86: Enable free running PEBS for REGS_USER/INTR")
Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
---
arch/x86/events/intel/core.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index df51c284cae4..9f957cf459bf 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -4032,7 +4032,9 @@ static unsigned long intel_pmu_large_pebs_flags(struct perf_event *event)
if (!event->attr.exclude_kernel)
flags &= ~PERF_SAMPLE_REGS_USER;
if (event->attr.sample_regs_user & ~PEBS_GP_REGS)
- flags &= ~(PERF_SAMPLE_REGS_USER | PERF_SAMPLE_REGS_INTR);
+ flags &= ~PERF_SAMPLE_REGS_USER;
+ if (event->attr.sample_regs_intr & ~PEBS_GP_REGS)
+ flags &= ~PERF_SAMPLE_REGS_INTR;
return flags;
}
--
2.43.0
next prev parent reply other threads:[~2025-06-26 3:42 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-23 22:35 [Patch v5 00/10] arch-PEBS enabling for Intel platforms Dapeng Mi
2025-06-23 22:35 ` [Patch v5 01/10] perf/x86/intel: Replace x86_pmu.drain_pebs calling with static call Dapeng Mi
2025-06-23 22:35 ` Dapeng Mi [this message]
2025-06-23 22:35 ` [Patch v5 03/10] perf/x86/intel: Initialize architectural PEBS Dapeng Mi
2025-06-23 22:35 ` [Patch v5 04/10] perf/x86/intel/ds: Factor out PEBS record processing code to functions Dapeng Mi
2025-06-23 22:35 ` [Patch v5 05/10] perf/x86/intel/ds: Factor out PEBS group " Dapeng Mi
2025-06-23 22:35 ` [Patch v5 06/10] perf/x86/intel: Process arch-PEBS records or record fragments Dapeng Mi
2025-06-23 22:35 ` [Patch v5 07/10] perf/x86/intel: Allocate arch-PEBS buffer and initialize PEBS_BASE MSR Dapeng Mi
2025-06-23 22:35 ` [Patch v5 08/10] perf/x86/intel: Update dyn_constranit base on PEBS event precise level Dapeng Mi
2025-06-23 22:35 ` [Patch v5 09/10] perf/x86/intel: Setup PEBS data configuration and enable legacy groups Dapeng Mi
2025-06-23 22:35 ` [Patch v5 10/10] perf/x86/intel: Add counter group support for arch-PEBS Dapeng Mi
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