From: Colton Lewis <coltonlewis@google.com>
To: kvm@vger.kernel.org
Cc: Paolo Bonzini <pbonzini@redhat.com>,
Jonathan Corbet <corbet@lwn.net>,
Russell King <linux@armlinux.org.uk>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>, Marc Zyngier <maz@kernel.org>,
Oliver Upton <oliver.upton@linux.dev>,
Mingwei Zhang <mizhang@google.com>,
Joey Gouly <joey.gouly@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Zenghui Yu <yuzenghui@huawei.com>,
Mark Rutland <mark.rutland@arm.com>,
Shuah Khan <shuah@kernel.org>,
linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev,
linux-perf-users@vger.kernel.org,
linux-kselftest@vger.kernel.org,
Colton Lewis <coltonlewis@google.com>
Subject: [PATCH v3 12/22] KVM: arm64: Use physical PMSELR for PMXEVTYPER if partitioned
Date: Thu, 26 Jun 2025 20:04:48 +0000 [thread overview]
Message-ID: <20250626200459.1153955-13-coltonlewis@google.com> (raw)
In-Reply-To: <20250626200459.1153955-1-coltonlewis@google.com>
Because PMXEVTYPER is trapped and PMSELR is not, it is not appropriate
to use the virtual PMSELR register when it could be outdated and lead
to an invalid write. Use the physical register.
Signed-off-by: Colton Lewis <coltonlewis@google.com>
---
arch/arm64/include/asm/arm_pmuv3.h | 7 ++++++-
arch/arm64/kvm/sys_regs.c | 9 +++++++--
2 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/include/asm/arm_pmuv3.h b/arch/arm64/include/asm/arm_pmuv3.h
index e2057365ba73..1880e426a559 100644
--- a/arch/arm64/include/asm/arm_pmuv3.h
+++ b/arch/arm64/include/asm/arm_pmuv3.h
@@ -72,11 +72,16 @@ static inline u64 read_pmcr(void)
return read_sysreg(pmcr_el0);
}
-static inline void write_pmselr(u32 val)
+static inline void write_pmselr(u64 val)
{
write_sysreg(val, pmselr_el0);
}
+static inline u64 read_pmselr(void)
+{
+ return read_sysreg(pmselr_el0);
+}
+
static inline void write_pmccntr(u64 val)
{
write_sysreg(val, pmccntr_el0);
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 49e8e3dcd306..771d73451b9a 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -1065,14 +1065,19 @@ static bool writethrough_pmevtyper(struct kvm_vcpu *vcpu, struct sys_reg_params
static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
const struct sys_reg_desc *r)
{
- u64 idx, reg;
+ u64 idx, reg, pmselr;
if (pmu_access_el0_disabled(vcpu))
return false;
if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) {
/* PMXEVTYPER_EL0 */
- idx = SYS_FIELD_GET(PMSELR_EL0, SEL, __vcpu_sys_reg(vcpu, PMSELR_EL0));
+ if (kvm_vcpu_pmu_is_partitioned(vcpu))
+ pmselr = read_pmselr();
+ else
+ pmselr = __vcpu_sys_reg(vcpu, PMSELR_EL0);
+
+ idx = SYS_FIELD_GET(PMSELR_EL0, SEL, pmselr);
reg = PMEVTYPER0_EL0 + idx;
} else if (r->CRn == 14 && (r->CRm & 12) == 12) {
idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
--
2.50.0.727.gbf7dc18ff4-goog
next prev parent reply other threads:[~2025-06-26 20:06 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-26 20:04 [PATCH v3 00/22] ARM64 PMU Partitioning Colton Lewis
2025-06-26 20:04 ` [PATCH v3 01/22] arm64: cpufeature: Add cpucap for HPMN0 Colton Lewis
2025-07-07 16:05 ` Mark Rutland
2025-07-08 22:34 ` Colton Lewis
2025-06-26 20:04 ` [PATCH v3 02/22] arm64: Generate sign macro for sysreg Enums Colton Lewis
2025-06-27 9:04 ` Ben Horgan
2025-06-27 20:45 ` Colton Lewis
2025-06-27 20:55 ` Oliver Upton
2025-06-30 17:42 ` Colton Lewis
2025-06-27 13:23 ` Marc Zyngier
2025-07-07 16:07 ` Mark Rutland
2025-06-26 20:04 ` [PATCH v3 03/22] KVM: arm64: Define PMI{CNTR,FILTR}_EL0 as undef_access Colton Lewis
2025-06-27 13:31 ` Marc Zyngier
2025-06-27 20:45 ` Colton Lewis
2025-06-26 20:04 ` [PATCH v3 04/22] KVM: arm64: Cleanup PMU includes Colton Lewis
2025-07-07 16:13 ` Mark Rutland
2025-07-08 22:37 ` Colton Lewis
2025-06-26 20:04 ` [PATCH v3 05/22] KVM: arm64: Reorganize PMU functions Colton Lewis
2025-06-26 20:04 ` [PATCH v3 06/22] perf: arm_pmuv3: Introduce method to partition the PMU Colton Lewis
2025-07-07 16:57 ` Mark Rutland
2025-07-07 19:07 ` Oliver Upton
2025-07-08 22:38 ` Colton Lewis
2025-07-08 22:41 ` Oliver Upton
2025-06-26 20:04 ` [PATCH v3 07/22] perf: arm_pmuv3: Generalize counter bitmasks Colton Lewis
2025-07-07 16:58 ` Mark Rutland
2025-07-08 22:38 ` Colton Lewis
2025-06-26 20:04 ` [PATCH v3 08/22] perf: arm_pmuv3: Keep out of guest counter partition Colton Lewis
2025-06-26 20:04 ` [PATCH v3 09/22] KVM: arm64: Correct kvm_arm_pmu_get_max_counters() Colton Lewis
2025-06-27 13:36 ` Marc Zyngier
2025-06-30 17:42 ` Colton Lewis
2025-06-26 20:04 ` [PATCH v3 10/22] KVM: arm64: Set up FGT for Partitioned PMU Colton Lewis
2025-06-27 15:01 ` Marc Zyngier
2025-06-27 20:45 ` Colton Lewis
2025-06-28 8:25 ` Marc Zyngier
2025-06-26 20:04 ` [PATCH v3 11/22] KVM: arm64: Writethrough trapped PMEVTYPER register Colton Lewis
2025-06-26 20:04 ` Colton Lewis [this message]
2025-06-26 20:04 ` [PATCH v3 13/22] KVM: arm64: Writethrough trapped PMOVS register Colton Lewis
2025-06-26 20:04 ` [PATCH v3 14/22] KVM: arm64: Write fast path PMU register handlers Colton Lewis
2025-06-26 20:04 ` [PATCH v3 15/22] KVM: arm64: Setup MDCR_EL2 to handle a partitioned PMU Colton Lewis
2025-06-26 20:04 ` [PATCH v3 16/22] KVM: arm64: Account for partitioning in PMCR_EL0 access Colton Lewis
2025-06-26 20:04 ` [PATCH v3 17/22] KVM: arm64: Context swap Partitioned PMU guest registers Colton Lewis
2025-06-26 20:04 ` [PATCH v3 18/22] KVM: arm64: Enforce PMU event filter at vcpu_load() Colton Lewis
2025-06-26 20:04 ` [PATCH v3 19/22] perf: arm_pmuv3: Handle IRQs for Partitioned PMU guest counters Colton Lewis
2025-06-26 20:04 ` [PATCH v3 20/22] KVM: arm64: Inject recorded guest interrupts Colton Lewis
2025-06-26 20:04 ` [PATCH v3 21/22] KVM: arm64: Add ioctl to partition the PMU when supported Colton Lewis
2025-06-26 20:04 ` [PATCH v3 22/22] KVM: arm64: selftests: Add test case for partitioned PMU Colton Lewis
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