From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pg1-f201.google.com (mail-pg1-f201.google.com [209.85.215.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7BA232BE7A2 for ; Wed, 6 Aug 2025 19:58:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754510301; cv=none; b=bpDtCtYmWB3nmxPu4NSIyJPV40kczMM1k99hZeyTKTpAu78k5jO5Cqa6uC2URjPyO/UJSz5K9sph+L54B4j0Yb6CDnrPsrDBULq1srSOJFtqOEjd2OduTA12h2eRb6vQof+dYf87eG0qFzYkWmMImOI1JIG00hthqRjNGHJ4mr8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754510301; c=relaxed/simple; bh=jAkcPQi41ZRUiWgI9bcgpSonHu4bIB2ojvxbKVROfG0=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=GyMxKh19zYB0h2nbDrnShhskv2+MuGynCMJ8lhDH89WtkCWBaAlUWX3Oqe1RhNig2RMDyzkYHhFZWQBWXNWfiUKrZn8to13mgbeVrqpPnTbcaic7i17e5ACdOoryoF5HXsDlQ/csAk8aqQ08Xo3TFa1lGABVMFJ8JcviteEtdBo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=TeRbBywX; arc=none smtp.client-ip=209.85.215.201 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="TeRbBywX" Received: by mail-pg1-f201.google.com with SMTP id 41be03b00d2f7-b4253124e77so125413a12.2 for ; Wed, 06 Aug 2025 12:58:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1754510297; x=1755115097; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=z6mRW3QO5+v30hMhQPo0nMlPZQjpAzxmFKtx3JiIrDs=; b=TeRbBywXy3/HckK5eGfsnHxSEh+9vQCZfspv9MpDXJ+LqCtFF9262mSffThUlNvyCZ MXeUSfvu3ECVvAy7YUXAM7HMOFML++5Jkn/Vkf3YU6xVzzx2szodilCsNapPiU7t5xXi Cv5T8NFMwzJGs4w3T0+dcpXb3EPeXX9BoL0L/jj5oi2dd2wBHMbG/5obSQtRRXJrSAdl JGGH9Umcl+Zxn8Ks1JY8aIZMTndtCqfCWbMbzwUmCw6dTf7Ra0VO4sIlM5Cbk/AZfkeb 68LxFjb7P3XeYDsZZWi9zxJMxRN3oBMj7Po5EOnXFmYiMe4+N9PgJsqcnFVurEUynlei iWBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1754510297; x=1755115097; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=z6mRW3QO5+v30hMhQPo0nMlPZQjpAzxmFKtx3JiIrDs=; b=nZOSERcymCrW9BUdVXCpYq3dTOiLBptKyp7Q7USmc6rVytHebqBpvuH16yIq3ZgHCQ D2q33kKqkq+aJVQw3PcynKaysITAtWAuKPdGDtfrpZS4c9EAS+iTIzNfhvy5nbcrkT/R WHHyBs3eDbNSKAY4G96pIWEvjZSnZAegTyXSEcZGHaUObtEyi/fP1RJQa5mpGR7dye8Y K8yYxX3tsHsmnIrJH/bqNfHqIAKpJE7PdfO0rZ+8D25mGqsvL95hohk3myhdUpXfxB35 DCQxnjq7Ek5EUvkM/ZAjO4pBsLVAeqhem/veHc50xSuI5g+/eCM3ALbqr61qnnUVDyGf ZHQA== X-Forwarded-Encrypted: i=1; AJvYcCXfntEtyvV9hIXHJiRx2sh/7tpDnFj9/LO0XlUGiWREMxkaBWa4BqVCo9R1dgXv2TOLPzHHF4KfTQtGHKEyXWD9@vger.kernel.org X-Gm-Message-State: AOJu0YyI1UqRN/N3eXetCCmBWwi17zgyC75kxpMdEc3q3lM8jE+DwZUL rcm5G1jtei6awhe1gHShnHvWN7OKI7gjhQ8F8dwB1Jo+Ncmr8eJ3A99kAlfOAa9XabIuvDL8qjQ tjNeaGw== X-Google-Smtp-Source: AGHT+IF1L5jDO3EJUjPLOXu/s6M1eVdU0dJDtzEbPUmRbyNFn2oUqefjt3C97kWpA7IvjzuPBYgNpNpIe1I= X-Received: from pgbcv5.prod.google.com ([2002:a05:6a02:4205:b0:b42:49c8:5488]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6a20:548d:b0:23f:faa0:2c27 with SMTP id adf61e73a8af0-240330367c3mr5937028637.20.1754510296766; Wed, 06 Aug 2025 12:58:16 -0700 (PDT) Reply-To: Sean Christopherson Date: Wed, 6 Aug 2025 12:56:48 -0700 In-Reply-To: <20250806195706.1650976-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250806195706.1650976-1-seanjc@google.com> X-Mailer: git-send-email 2.50.1.565.gc32cd1483b-goog Message-ID: <20250806195706.1650976-27-seanjc@google.com> Subject: [PATCH v5 26/44] KVM: VMX: Add helpers to toggle/change a bit in VMCS execution controls From: Sean Christopherson To: Marc Zyngier , Oliver Upton , Tianrui Zhao , Bibo Mao , Huacai Chen , Anup Patel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Xin Li , "H. Peter Anvin" , Andy Lutomirski , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Sean Christopherson , Paolo Bonzini Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, loongarch@lists.linux.dev, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Kan Liang , Yongwei Ma , Mingwei Zhang , Xiong Zhang , Sandipan Das , Dapeng Mi Content-Type: text/plain; charset="UTF-8" From: Dapeng Mi Expand the VMCS controls builder macros to generate helpers to change a bit to the desired value, and use the new helpers when toggling APICv related controls. No functional change intended. Suggested-by: Sean Christopherson Signed-off-by: Dapeng Mi Signed-off-by: Mingwei Zhang [sean: rewrite changelog] Signed-off-by: Sean Christopherson --- arch/x86/kvm/vmx/vmx.c | 20 +++++++------------- arch/x86/kvm/vmx/vmx.h | 8 ++++++++ 2 files changed, 15 insertions(+), 13 deletions(-) diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 6094de4855d6..baea4a9cf74f 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -4356,19 +4356,13 @@ void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu) pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx)); - if (kvm_vcpu_apicv_active(vcpu)) { - secondary_exec_controls_setbit(vmx, - SECONDARY_EXEC_APIC_REGISTER_VIRT | - SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); - if (enable_ipiv) - tertiary_exec_controls_setbit(vmx, TERTIARY_EXEC_IPI_VIRT); - } else { - secondary_exec_controls_clearbit(vmx, - SECONDARY_EXEC_APIC_REGISTER_VIRT | - SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); - if (enable_ipiv) - tertiary_exec_controls_clearbit(vmx, TERTIARY_EXEC_IPI_VIRT); - } + secondary_exec_controls_changebit(vmx, + SECONDARY_EXEC_APIC_REGISTER_VIRT | + SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY, + kvm_vcpu_apicv_active(vcpu)); + if (enable_ipiv) + tertiary_exec_controls_changebit(vmx, TERTIARY_EXEC_IPI_VIRT, + kvm_vcpu_apicv_active(vcpu)); vmx_update_msr_bitmap_x2apic(vcpu); } diff --git a/arch/x86/kvm/vmx/vmx.h b/arch/x86/kvm/vmx/vmx.h index d3389baf3ab3..a4e5bcd1d023 100644 --- a/arch/x86/kvm/vmx/vmx.h +++ b/arch/x86/kvm/vmx/vmx.h @@ -608,6 +608,14 @@ static __always_inline void lname##_controls_clearbit(struct vcpu_vmx *vmx, u##b { \ BUILD_BUG_ON(!(val & (KVM_REQUIRED_VMX_##uname | KVM_OPTIONAL_VMX_##uname))); \ lname##_controls_set(vmx, lname##_controls_get(vmx) & ~val); \ +} \ +static __always_inline void lname##_controls_changebit(struct vcpu_vmx *vmx, u##bits val, \ + bool set) \ +{ \ + if (set) \ + lname##_controls_setbit(vmx, val); \ + else \ + lname##_controls_clearbit(vmx, val); \ } BUILD_CONTROLS_SHADOW(vm_entry, VM_ENTRY_CONTROLS, 32) BUILD_CONTROLS_SHADOW(vm_exit, VM_EXIT_CONTROLS, 32) -- 2.50.1.565.gc32cd1483b-goog