From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pg1-f180.google.com (mail-pg1-f180.google.com [209.85.215.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2FD9B2DE718; Mon, 11 Aug 2025 13:55:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.180 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754920560; cv=none; b=Rd8hMVDVfzpxvpz1f+qI+hOjIR5xSBE6U2+FTsx+sYoAAml3UghW7IzciA+DJcHkOvOejZzRlmy0zo8Lmqxb+TzU60QfSgla6v4JQfVEkgjgWuA8WpH1J7HuK7znT9Rmawfdz+9DcndhlsVOaPo6fP/lo69uj1nPNjOHJgST5nA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754920560; c=relaxed/simple; bh=+LJO62oOzNOE3W3QjbhqRWaYWvRbJogCNl2YzLIGJDM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=C4ou72zG4x6Zvy9bkoo6Oe6mrLazvWBFPaGMonBYcQDgeqPoq9639943e7y3uZ9xglFYDhSkWIBleTPy6GkvmCm6vUq5tTmA5F4pq3vD9IZ7Z8GTry+1wDZYf0GYyNIg8nLMJOP2P+8UP59Jiq9wXsvlgxknfKKV3j/SaKQtwpg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=ZTVr/MHF; arc=none smtp.client-ip=209.85.215.180 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ZTVr/MHF" Received: by mail-pg1-f180.google.com with SMTP id 41be03b00d2f7-b26f7d2c1f1so4679593a12.0; Mon, 11 Aug 2025 06:55:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1754920558; x=1755525358; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=ekIJRrV1jgTknYSabjgcGw65AB4pALQ0leG5PtMd0ws=; b=ZTVr/MHFx39P2XK8pc0//vsfN6+JSykpDEUce1kvyUqvkVAx0qa4dHy59QS7Z2YYv9 MsbRrpiKoB936kI42NGbL4LSJiys4AYvUQTSzNB5rKQqPMIr7LaOwQ/Bzzx6FjYhL13O OKKLWYrlNPmQzfDUmzfKwN0LzsvqRKiyDiI6UmSJNU1M/MB+LBp+EeeGKWynnwSM7x1m GkmU9lq6dpE4GCF19Igc4pDlQfydsUftsaIdb3/8R0nJpCxM/IngtY8G9IN3tKJQK0MK HT12TsQUex69dDfr8RizHl11XVO3WjmGQjGrjp5NsesDejCtd6wnxf0I2wwOOF/hyCoT QO4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1754920558; x=1755525358; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ekIJRrV1jgTknYSabjgcGw65AB4pALQ0leG5PtMd0ws=; b=FwtbG6Cbu11NOX2TaTnEiZ9GP1uD0RCOYAEfdoQQL431u+mQoj8M7oP5r+z0SY7kIN RAhq+xtXaryhwikF/DSCM1vyCV13znQ7KdqI+QRjxTwtChwyqcuvVcXX9lo0T0U2C8/b GH6gvrxIF57DVUL8X2oL+VCSXphbQTbUudlyMNmwRz+HynaCspWoNyRc0pQ+1qO10+aE LNbcj51yx4WSz4sLzgG7CbZ6A8N+YktiiC/g2YOScrI42CMydbip0jNfuP+u+L9V4tMI wv8m8QLQYPMBxFEiB1bPliDJYGkdXPgzYp8cNKGePZqB6E421JqHEVF7HuxN97nf4PBe CepA== X-Forwarded-Encrypted: i=1; AJvYcCWBeRfX6ro+SNGuGco7+AI6RG+BGLY//e3nh+WUqQz4f9uR3TvHkUZ0PenJkN+8JFvfFZavVgOUO87T@vger.kernel.org, AJvYcCWc2EtXd32dARCMjjQUxEQuXHDJGlk2jnQjn5pD3Op0paDC472kRwsRUQ0/I7mVO1IMczTVT6qL7sBZ0i/n@vger.kernel.org, AJvYcCXkjA5hOLiboHcfX3hZHLujz4KDabKMK7s0S9qq38ftzWu9SoXo5Oxwbr4VD9qJED3MPW1XjEIJBN6CrEFsOS1N9g==@vger.kernel.org X-Gm-Message-State: AOJu0YxyEXJkoV3sDJNRlrQhwAjKq5a1gYjWTUBn6BvyZiroDLrq7kAz uw+IpDbgmquul46gg36SQ0qkO+dAfaVBsIC+v2FvofV//AK5RsI+6G1t X-Gm-Gg: ASbGncuKY2ayuhT2s8++rAOzn3NO+e6FAceROPH2XppGD9KwVOAlr6C4GgSnlON4GPZ /A7zQ1SYnrpIF1YiAfZi1shoWNfpn/MvTajJ8tTHFAxiGfJBNwKWCs0s0LaZsQl6tuk1uoSdAy1 r8VZPQVbkeLOsR/2e0R1jhDSM3mYIznlFvgA58YBWcklBVtxfikyQ9bth62YWHPZw8fDsSskQFV q7QtRBcKPhlLcRTR/ov6gTzWqcOLxVmaDxArJnzIl9lXpb9bRhMb4tHCrRRRIVmWW+6UNahoIlV YtKnC+O/l0eIt4G6Z8cyU3JiPLlAx2D8a9QsTb5hZsmVkitqA228BN15iu8WVP4LMpfOeUpsXvZ TEd7MGOE0h/6VGMiK3UBEfyelOq4/t0iHEKINmG18GebeAM8= X-Google-Smtp-Source: AGHT+IGsMUs7rZT6EfgZsbIZw5UoMuCPkGY9qydxlX8Psd6B1G0iWToWEEsbMJteFeHMDxlHyQ13Nw== X-Received: by 2002:a17:90b:3e84:b0:31f:20d4:9966 with SMTP id 98e67ed59e1d1-32183e33797mr20579663a91.17.1754920558250; Mon, 11 Aug 2025 06:55:58 -0700 (PDT) Received: from [127.0.1.1] (061092221177.ctinets.com. [61.92.221.177]) by smtp.googlemail.com with ESMTPSA id 41be03b00d2f7-b422bb1133fsm23585496a12.56.2025.08.11.06.55.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Aug 2025 06:55:57 -0700 (PDT) From: Nick Chan Date: Mon, 11 Aug 2025 21:54:40 +0800 Subject: [PATCH v8 08/21] drivers/perf: apple_m1: Add Apple A7 support Precedence: bulk X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20250811-apple-cpmu-v8-8-c560ebd9ca46@gmail.com> References: <20250811-apple-cpmu-v8-0-c560ebd9ca46@gmail.com> In-Reply-To: <20250811-apple-cpmu-v8-0-c560ebd9ca46@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Sven Peter Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=11055; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=+LJO62oOzNOE3W3QjbhqRWaYWvRbJogCNl2YzLIGJDM=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBomfZBkx5s7RXQXmDlTeJTFIVAfIwR+nU8o+5ef 1flYi+l8BeJAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaJn2QQAKCRABygi3psUI JA7uEACZFAUWLVhZKPGWt7tBn0+XI+y5gRUC4olpNQoLLxXMLtZbPzViF4gu4hIKTSligv0k1NY r4lIfI3VPKxI/wr/vJMveKvroMRJv+xTDcilLTk33/Eew3TMXHGTflVzA49WWxZGCVg3RE+wSHX g1f4zir9+Wsop8/RzjXHnMHiKf13EYJNwukw1aSYt1aQV8RAsxSOlfsDkIfOMuz/eN+CH0XxRR+ 2sSTfqPNPONQrvhVbxTzEZJOWhXwCFMefdhFUzR5r5PvE22p0fIOP3mYkFZgdOmiTg5ZFdq2xCj f2ndVkY/YyOE4nmmORJrQUhr+Zd7fUNrk950eymuHRdtjKMq9O81+pev+KjIIejp0rSEbnrqxFU 7ov05jEm6q9kCsnJU/XPSH+TMwk2qsHQB0n/DjOwMtgo6KPmgkHFPc3QVsnPk2VKZdXFyIqem6t IlEa6J6ErYxaGMKqOOgN+0pRrmJf9JtqZXskThwx1rmy5VxCBc/ZfQaVGzEbiwAH62PjJYw+rmJ bXvVlxE/5HzGmf7KHQwJFXr0Cqty7TXdwInWJZtSZkCZfHR2LGXYLHVSHBerlhTivvg8V/m5ewp 6k+qxj8vmr/gS0+EnL1ONgm1Rv0UFkeO63194PnQIZmaqig8oZZIRuBwjivD09tfnDNg3hsVeLm aTviJzVkT0ilYqA== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Add support for the CPU PMU found in the Apple A7 SoC. The PMU has 8 counters and a very different event layout compared to the M1 PMU. Interrupts are delivered as IRQs instead of FIQs like on the M1. Signed-off-by: Nick Chan --- drivers/perf/apple_m1_cpu_pmu.c | 190 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 190 insertions(+) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pmu.c index d0362a1813788776f4210523efe33a3018cfef2a..afcf7c951379698ceff21c1a99cca31b3a6177b1 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -19,6 +19,7 @@ #include #include +#define A7_PMU_NR_COUNTERS 8 #define M1_PMU_NR_COUNTERS 10 #define APPLE_PMU_MAX_NR_COUNTERS 10 @@ -45,6 +46,143 @@ * know next to nothing about the events themselves, and we already have * per cpu-type PMU abstractions. */ + +enum a7_pmu_events { + A7_PMU_PERFCTR_INST_ALL = 0x0, + A7_PMU_PERFCTR_UNKNOWN_1 = 0x1, + A7_PMU_PERFCTR_CORE_ACTIVE_CYCLE = 0x2, + A7_PMU_PERFCTR_L2_TLB_MISS_INSTRUCTION = 0x10, + A7_PMU_PERFCTR_L2_TLB_MISS_DATA = 0x11, + A7_PMU_PERFCTR_BIU_UPSTREAM_CYCLE = 0x19, + A7_PMU_PERFCTR_BIU_DOWNSTREAM_CYCLE = 0x20, + A7_PMU_PERFCTR_L2C_AGENT_LD = 0x22, + A7_PMU_PERFCTR_L2C_AGENT_LD_MISS = 0x23, + A7_PMU_PERFCTR_L2C_AGENT_ST = 0x24, + A7_PMU_PERFCTR_L2C_AGENT_ST_MISS = 0x25, + A7_PMU_PERFCTR_SCHEDULE_UOP = 0x58, + A7_PMU_PERFCTR_MAP_REWIND = 0x61, + A7_PMU_PERFCTR_MAP_STALL = 0x62, + A7_PMU_PERFCTR_FLUSH_RESTART_OTHER_NONSPEC = 0x6e, + A7_PMU_PERFCTR_INST_A32 = 0x78, + A7_PMU_PERFCTR_INST_T32 = 0x79, + A7_PMU_PERFCTR_INST_A64 = 0x7a, + A7_PMU_PERFCTR_INST_BRANCH = 0x7b, + A7_PMU_PERFCTR_INST_BRANCH_CALL = 0x7c, + A7_PMU_PERFCTR_INST_BRANCH_RET = 0x7d, + A7_PMU_PERFCTR_INST_BRANCH_TAKEN = 0x7e, + A7_PMU_PERFCTR_INST_BRANCH_INDIR = 0x81, + A7_PMU_PERFCTR_INST_BRANCH_COND = 0x82, + A7_PMU_PERFCTR_INST_INT_LD = 0x83, + A7_PMU_PERFCTR_INST_INT_ST = 0x84, + A7_PMU_PERFCTR_INST_INT_ALU = 0x85, + A7_PMU_PERFCTR_INST_SIMD_LD = 0x86, + A7_PMU_PERFCTR_INST_SIMD_ST = 0x87, + A7_PMU_PERFCTR_INST_SIMD_ALU = 0x88, + A7_PMU_PERFCTR_INST_LDST = 0x89, + A7_PMU_PERFCTR_UNKNOWN_8d = 0x8d, + A7_PMU_PERFCTR_UNKNOWN_8e = 0x8e, + A7_PMU_PERFCTR_UNKNOWN_8f = 0x8f, + A7_PMU_PERFCTR_UNKNOWN_90 = 0x90, + A7_PMU_PERFCTR_UNKNOWN_93 = 0x93, + A7_PMU_PERFCTR_UNKNOWN_94 = 0x94, + A7_PMU_PERFCTR_UNKNOWN_95 = 0x95, + A7_PMU_PERFCTR_L1D_TLB_ACCESS = 0x96, + A7_PMU_PERFCTR_L1D_TLB_MISS = 0x97, + A7_PMU_PERFCTR_L1D_CACHE_MISS_ST = 0x98, + A7_PMU_PERFCTR_L1D_CACHE_MISS_LD = 0x99, + A7_PMU_PERFCTR_UNKNOWN_9b = 0x9b, + A7_PMU_PERFCTR_LD_UNIT_UOP = 0x9c, + A7_PMU_PERFCTR_ST_UNIT_UOP = 0x9d, + A7_PMU_PERFCTR_L1D_CACHE_WRITEBACK = 0x9e, + A7_PMU_PERFCTR_UNKNOWN_9f = 0x9f, + A7_PMU_PERFCTR_LDST_X64_UOP = 0xa7, + A7_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC = 0xb4, + A7_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC = 0xb5, + A7_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC = 0xb6, + A7_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC = 0xb9, + A7_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC = 0xba, + A7_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC = 0xbb, + A7_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC = 0xbd, + A7_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC = 0xbf, + A7_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC = 0xc0, + A7_PMU_PERFCTR_UNKNOWN_c1 = 0xc1, + A7_PMU_PERFCTR_UNKNOWN_c4 = 0xc4, + A7_PMU_PERFCTR_UNKNOWN_c5 = 0xc5, + A7_PMU_PERFCTR_UNKNOWN_c6 = 0xc6, + A7_PMU_PERFCTR_UNKNOWN_c8 = 0xc8, + A7_PMU_PERFCTR_UNKNOWN_ca = 0xca, + A7_PMU_PERFCTR_UNKNOWN_cb = 0xcb, + A7_PMU_PERFCTR_FED_IC_MISS_DEMAND = 0xce, + A7_PMU_PERFCTR_L1I_TLB_MISS_DEMAND = 0xcf, + A7_PMU_PERFCTR_UNKNOWN_f5 = 0xf5, + A7_PMU_PERFCTR_UNKNOWN_f6 = 0xf6, + A7_PMU_PERFCTR_UNKNOWN_f7 = 0xf7, + A7_PMU_PERFCTR_UNKNOWN_f8 = 0xf8, + A7_PMU_PERFCTR_UNKNOWN_fd = 0xfd, + A7_PMU_PERFCTR_LAST = M1_PMU_CFG_EVENT, + /* + * From this point onwards, these are not actual HW events, + * but attributes that get stored in hw->config_base. + */ + A7_PMU_CFG_COUNT_USER = BIT(8), + A7_PMU_CFG_COUNT_KERNEL = BIT(9), +}; + +static const u16 a7_pmu_event_affinity[A7_PMU_PERFCTR_LAST + 1] = { + [0 ... A7_PMU_PERFCTR_LAST] = ANY_BUT_0_1, + [A7_PMU_PERFCTR_INST_ALL] = ANY_BUT_0_1 | BIT(1), + [A7_PMU_PERFCTR_UNKNOWN_1] = ONLY_5_6_7, + [A7_PMU_PERFCTR_CORE_ACTIVE_CYCLE] = ANY_BUT_0_1 | BIT(0), + [A7_PMU_PERFCTR_INST_A32] = ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_T32] = ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_A64] = ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_BRANCH] = ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_BRANCH_CALL] = ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_BRANCH_RET] = ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_BRANCH_TAKEN] = ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_BRANCH_INDIR] = ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_BRANCH_COND] = ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_INT_LD] = ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_INT_ST] = ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_INT_ALU] = ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_SIMD_LD] = ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_SIMD_ST] = ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_SIMD_ALU] = ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_LDST] = ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_8d] = ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_8e] = ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_8f] = ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_90] = ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_93] = ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_94] = ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_95] = ONLY_5_6_7, + [A7_PMU_PERFCTR_L1D_CACHE_MISS_ST] = ONLY_5_6_7, + [A7_PMU_PERFCTR_L1D_CACHE_MISS_LD] = ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_9b] = ONLY_5_6_7, + [A7_PMU_PERFCTR_LD_UNIT_UOP] = ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_9f] = ONLY_5_6_7, + [A7_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC] = ONLY_5_6_7, + [A7_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC] = ONLY_5_6_7, + [A7_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC] = ONLY_5_6_7, + [A7_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC] = ONLY_5_6_7, + [A7_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC] = ONLY_5_6_7, + [A7_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC] = ONLY_5_6_7, + [A7_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC] = ONLY_5_6_7, + [A7_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC] = ONLY_5_6_7, + [A7_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC] = ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_c1] = ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_c4] = ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_c5] = ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_c6] = ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_c8] = ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_ca] = ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_cb] = ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_f5] = ONLY_2_4_6, + [A7_PMU_PERFCTR_UNKNOWN_f6] = ONLY_2_4_6, + [A7_PMU_PERFCTR_UNKNOWN_f7] = ONLY_2_4_6, + [A7_PMU_PERFCTR_UNKNOWN_fd] = ONLY_2_4_6, +}; + enum m1_pmu_events { M1_PMU_PERFCTR_RETIRE_UOP = 0x1, M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE = 0x2, @@ -165,6 +303,14 @@ static const u16 m1_pmu_event_affinity[M1_PMU_PERFCTR_LAST + 1] = { [M1_PMU_PERFCTR_UNKNOWN_fd] = ONLY_2_4_6, }; +static const unsigned int a7_pmu_perf_map[PERF_COUNT_HW_MAX] = { + PERF_MAP_ALL_UNSUPPORTED, + [PERF_COUNT_HW_CPU_CYCLES] = A7_PMU_PERFCTR_CORE_ACTIVE_CYCLE, + [PERF_COUNT_HW_INSTRUCTIONS] = A7_PMU_PERFCTR_INST_ALL, + [PERF_COUNT_HW_BRANCH_MISSES] = A7_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC, + [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = A7_PMU_PERFCTR_INST_BRANCH +}; + static const unsigned m1_pmu_perf_map[PERF_COUNT_HW_MAX] = { PERF_MAP_ALL_UNSUPPORTED, [PERF_COUNT_HW_CPU_CYCLES] = M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE, @@ -199,6 +345,17 @@ static ssize_t m1_pmu_events_sysfs_show(struct device *dev, #define M1_PMU_EVENT_ATTR(name, config) \ PMU_EVENT_ATTR_ID(name, m1_pmu_events_sysfs_show, config) +static struct attribute *a7_pmu_event_attrs[] = { + M1_PMU_EVENT_ATTR(cycles, A7_PMU_PERFCTR_CORE_ACTIVE_CYCLE), + M1_PMU_EVENT_ATTR(instructions, A7_PMU_PERFCTR_INST_ALL), + NULL, +}; + +static const struct attribute_group a7_pmu_events_attr_group = { + .name = "events", + .attrs = a7_pmu_event_attrs, +}; + static struct attribute *m1_pmu_event_attrs[] = { M1_PMU_EVENT_ATTR(cycles, M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE), M1_PMU_EVENT_ATTR(instructions, M1_PMU_PERFCTR_INST_ALL), @@ -521,6 +678,12 @@ static int apple_pmu_get_event_idx(struct pmu_hw_events *cpuc, return -EAGAIN; } +static int a7_pmu_get_event_idx(struct pmu_hw_events *cpuc, + struct perf_event *event) +{ + return apple_pmu_get_event_idx(cpuc, event, a7_pmu_event_affinity); +} + static int m1_pmu_get_event_idx(struct pmu_hw_events *cpuc, struct perf_event *event) { @@ -544,6 +707,11 @@ static void __m1_pmu_set_mode(u8 mode) isb(); } +static void a7_pmu_start(struct arm_pmu *cpu_pmu) +{ + __m1_pmu_set_mode(PMCR0_IMODE_AIC); +} + static void m1_pmu_start(struct arm_pmu *cpu_pmu) { __m1_pmu_set_mode(PMCR0_IMODE_FIQ); @@ -578,6 +746,11 @@ static int apple_pmu_map_event_63(struct perf_event *event, return armpmu_map_event(event, perf_map, NULL, M1_PMU_CFG_EVENT); } +static int a7_pmu_map_event(struct perf_event *event) +{ + return apple_pmu_map_event_47(event, &a7_pmu_perf_map); +} + static int m1_pmu_map_event(struct perf_event *event) { return apple_pmu_map_event_47(event, &m1_pmu_perf_map); @@ -623,6 +796,11 @@ static void apple_pmu_reset(void *info, u32 counters) isb(); } +static void a7_pmu_reset(void *info) +{ + apple_pmu_reset(info, A7_PMU_NR_COUNTERS); +} + static void m1_pmu_reset(void *info) { apple_pmu_reset(info, M1_PMU_NR_COUNTERS); @@ -673,6 +851,17 @@ static int apple_pmu_init(struct arm_pmu *cpu_pmu, u32 counters) } /* Device driver gunk */ +static int a7_pmu_cyclone_init(struct arm_pmu *cpu_pmu) +{ + cpu_pmu->name = "apple_cyclone_pmu"; + cpu_pmu->get_event_idx = a7_pmu_get_event_idx; + cpu_pmu->map_event = a7_pmu_map_event; + cpu_pmu->reset = a7_pmu_reset; + cpu_pmu->start = a7_pmu_start; + cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = &a7_pmu_events_attr_group; + return apple_pmu_init(cpu_pmu, A7_PMU_NR_COUNTERS); +} + static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu) { cpu_pmu->name = "apple_icestorm_pmu"; @@ -722,6 +911,7 @@ static const struct of_device_id m1_pmu_of_device_ids[] = { { .compatible = "apple,blizzard-pmu", .data = m2_pmu_blizzard_init, }, { .compatible = "apple,icestorm-pmu", .data = m1_pmu_ice_init, }, { .compatible = "apple,firestorm-pmu", .data = m1_pmu_fire_init, }, + { .compatible = "apple,cyclone-pmu", .data = a7_pmu_cyclone_init, }, { }, }; MODULE_DEVICE_TABLE(of, m1_pmu_of_device_ids); -- 2.50.1