[PATCH 0/4] perf arm-spe: Improve --itrace options

[PATCH 0/4] perf arm-spe: Improve --itrace options

[James Clark]

Most people also want all the SPE samples (instructions group), not just
the flagged samples that are put into the various memory groups. These
should have been shown by default but weren't because the default
interval type wasn't supported.

Also when looking at this, it appears that the downsampling was behaving
in a way that would discard samples from one group but not another.
Improve that and the warning messages.

I don't want to put fixes tags on these because it's only changing the
defaults and the behavior, but I don't think the previous behavior was
incorrect necessarily, just copied from tracing techs but not ideal for
SPE.

Signed-off-by: James Clark <james.clark@linaro.org>
---
James Clark (4):
      perf arm-spe: Show instruction sample types by default
      perf arm-spe: Downsample all sample types equally
      perf arm-spe: Display --itrace period warnings for all sample types
      perf docs: Update SPE doc to include default instructions group

 tools/perf/Documentation/perf-arm-spe.txt | 14 +++++---
 tools/perf/util/arm-spe.c                 | 53 ++++++++++++++++---------------
 2 files changed, 37 insertions(+), 30 deletions(-)
---
base-commit: 75a7b9d29215c5aa813b9620f3c56817918f9f8c
change-id: 20250908-james-perf-spe-period-4711a566cba4

Best regards,
-- 
James Clark <james.clark@linaro.org>

[PATCH 1/4] perf arm-spe: Show instruction sample types by default

[James Clark]

Instruction sample types are enabled in the default itrace options in
Perf, but this never applied to SPE because the default nanoseconds
period isn't supported. This meant that instructions ended up being
opt-in by the user only when they requested an instruction based period.

Change the default period type to instructions so that instruction
samples are generated by default. This can overridden by specifying any
--itrace option.

This solves a common complaint from users that the unfiltered SPE
samples appear to be missing, and only the samples that have memory
flags set appear in the various memory groups.

Signed-off-by: James Clark <james.clark@linaro.org>
---
 tools/perf/util/arm-spe.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c
index 8942fa598a84..b33a0a170ef8 100644
--- a/tools/perf/util/arm-spe.c
+++ b/tools/perf/util/arm-spe.c
@@ -1871,10 +1871,14 @@ int arm_spe_process_auxtrace_info(union perf_event *event,
 	if (dump_trace)
 		return 0;
 
-	if (session->itrace_synth_opts && session->itrace_synth_opts->set)
+	if (session->itrace_synth_opts && session->itrace_synth_opts->set) {
 		spe->synth_opts = *session->itrace_synth_opts;
-	else
+	} else {
 		itrace_synth_opts__set_default(&spe->synth_opts, false);
+		/* Default nanoseconds period not supported */
+		spe->synth_opts.period_type = PERF_ITRACE_PERIOD_INSTRUCTIONS;
+		spe->synth_opts.period = 1;
+	}
 
 	err = arm_spe_synth_events(spe, session);
 	if (err)

-- 
2.34.1

[PATCH 2/4] perf arm-spe: Downsample all sample types equally

[James Clark]

The various sample types that are generated are based on the same SPE
sample, just placed into different sample type bins. The same sample can
be in multiple bins if it has flags set that cause it to be.

Currently we're only applying the --itrace interval downsampling to the
instruction bin, which means that the sample would appear in one bin but
not another if it was skipped due to downsampling. I don't thing anyone
would want or expect this, so make this behave consistently by applying
the downsampling before generating any sample.

You might argue that the "instructions" interval type doesn't make sense
to apply to "memory" sample types because it would be skipping every n
memory samples, rather than every n instructions. But the downsampling
was already not an instruction interval even for the instruction
samples. SPE has a hardware based sampling interval, and the instruction
interval was just a convenient way to specify further downsampling. This
is hinted at in the warning message shown for intervals greater than 1.

This makes SPE diverge from trace technologies like Intel PT and Arm
Coresight. In those cases instruction samples can be reduced but all
branches are still emitted. This makes sense there, because branches
form a complete execution history, and asking to skip branches every n
instructions doesn't really make sense. But for SPE, as mentioned above,
downsampling the instruction samples already wasn't consistent with
trace technologies so we ended up with some middle ground that had no
benefit. Now it's possible to reduce the volume of samples in all groups
and samples won't be missing from one group but present in another.

Signed-off-by: James Clark <james.clark@linaro.org>
---
 tools/perf/util/arm-spe.c | 27 ++++++++++++---------------
 1 file changed, 12 insertions(+), 15 deletions(-)

diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c
index b33a0a170ef8..4c81518a033a 100644
--- a/tools/perf/util/arm-spe.c
+++ b/tools/perf/util/arm-spe.c
@@ -62,7 +62,6 @@ struct arm_spe {
 	u8				sample_remote_access;
 	u8				sample_memory;
 	u8				sample_instructions;
-	u64				instructions_sample_period;
 
 	u64				l1d_miss_id;
 	u64				l1d_access_id;
@@ -101,7 +100,7 @@ struct arm_spe_queue {
 	u64				time;
 	u64				timestamp;
 	struct thread			*thread;
-	u64				period_instructions;
+	u64				sample_count;
 	u32				flags;
 	struct branch_stack		*last_branch;
 };
@@ -228,7 +227,6 @@ static struct arm_spe_queue *arm_spe__alloc_queue(struct arm_spe *spe,
 	speq->pid = -1;
 	speq->tid = -1;
 	speq->cpu = -1;
-	speq->period_instructions = 0;
 
 	/* params set */
 	params.get_trace = arm_spe_get_trace;
@@ -352,7 +350,7 @@ static void arm_spe_prep_sample(struct arm_spe *spe,
 	sample->cpumode = arm_spe_cpumode(spe, sample->ip);
 	sample->pid = speq->pid;
 	sample->tid = speq->tid;
-	sample->period = 1;
+	sample->period = spe->synth_opts.period;
 	sample->cpu = speq->cpu;
 	sample->simd_flags = arm_spe__synth_simd_flags(record);
 
@@ -527,14 +525,6 @@ static int arm_spe__synth_instruction_sample(struct arm_spe_queue *speq,
 	struct perf_sample sample;
 	int ret;
 
-	/*
-	 * Handles perf instruction sampling period.
-	 */
-	speq->period_instructions++;
-	if (speq->period_instructions < spe->instructions_sample_period)
-		return 0;
-	speq->period_instructions = 0;
-
 	perf_sample__init(&sample, /*all=*/true);
 	arm_spe_prep_sample(spe, speq, event, &sample);
 
@@ -543,7 +533,6 @@ static int arm_spe__synth_instruction_sample(struct arm_spe_queue *speq,
 	sample.addr = record->to_ip;
 	sample.phys_addr = record->phys_addr;
 	sample.data_src = data_src;
-	sample.period = spe->instructions_sample_period;
 	sample.weight = record->latency;
 	sample.flags = speq->flags;
 	sample.branch_stack = speq->last_branch;
@@ -929,6 +918,14 @@ static int arm_spe_sample(struct arm_spe_queue *speq)
 	u64 data_src;
 	int err;
 
+	/*
+	 * Discard all samples until period is reached
+	 */
+	speq->sample_count++;
+	if (speq->sample_count < spe->synth_opts.period)
+		return 0;
+	speq->sample_count = 0;
+
 	arm_spe__sample_flags(speq);
 	data_src = arm_spe__synth_data_source(speq, record);
 
@@ -1628,6 +1625,7 @@ arm_spe_synth_events(struct arm_spe *spe, struct perf_session *session)
 	attr.exclude_guest = evsel->core.attr.exclude_guest;
 	attr.sample_id_all = evsel->core.attr.sample_id_all;
 	attr.read_format = evsel->core.attr.read_format;
+	attr.sample_period = spe->synth_opts.period;
 
 	/* create new id val to be a fixed offset from evsel id */
 	id = evsel->core.id[0] + 1000000000;
@@ -1754,8 +1752,7 @@ arm_spe_synth_events(struct arm_spe *spe, struct perf_session *session)
 
 		spe->sample_instructions = true;
 		attr.config = PERF_COUNT_HW_INSTRUCTIONS;
-		attr.sample_period = spe->synth_opts.period;
-		spe->instructions_sample_period = attr.sample_period;
+
 		err = perf_session__deliver_synth_attr_event(session, &attr, id);
 		if (err)
 			return err;

-- 
2.34.1

[PATCH 3/4] perf arm-spe: Display --itrace period warnings for all sample types

[James Clark]

Currently we only display the warning when the instructions group is
requested. Instructions are on by default, and the period applies to all
sample types anyway so always check the options and show the warning.

Reword the messages to be more explicit about which flags the warnings
apply to.

Signed-off-by: James Clark <james.clark@linaro.org>
---
 tools/perf/util/arm-spe.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c
index 4c81518a033a..228ed52e653d 100644
--- a/tools/perf/util/arm-spe.c
+++ b/tools/perf/util/arm-spe.c
@@ -1742,14 +1742,6 @@ arm_spe_synth_events(struct arm_spe *spe, struct perf_session *session)
 	}
 
 	if (spe->synth_opts.instructions) {
-		if (spe->synth_opts.period_type != PERF_ITRACE_PERIOD_INSTRUCTIONS) {
-			pr_warning("Only instruction-based sampling period is currently supported by Arm SPE.\n");
-			goto synth_instructions_out;
-		}
-		if (spe->synth_opts.period > 1)
-			pr_warning("Arm SPE has a hardware-based sample period.\n"
-				   "Additional instruction events will be discarded by --itrace\n");
-
 		spe->sample_instructions = true;
 		attr.config = PERF_COUNT_HW_INSTRUCTIONS;
 
@@ -1759,7 +1751,6 @@ arm_spe_synth_events(struct arm_spe *spe, struct perf_session *session)
 		spe->instructions_id = id;
 		arm_spe_set_event_name(evlist, id, "instructions");
 	}
-synth_instructions_out:
 
 	return 0;
 }
@@ -1877,6 +1868,15 @@ int arm_spe_process_auxtrace_info(union perf_event *event,
 		spe->synth_opts.period = 1;
 	}
 
+	if (spe->synth_opts.period_type != PERF_ITRACE_PERIOD_INSTRUCTIONS) {
+		ui__error("You must only use i (instructions) --itrace period with Arm SPE. e.g --itrace=i1i\n");
+		err = -EINVAL;
+		goto err_free_queues;
+	}
+	if (spe->synth_opts.period > 1)
+		ui__warning("Arm SPE has a hardware-based sampling period.\n\n"
+			    "--itrace periods > 1i downsample by an interval of n SPE samples rather than n instructions.\n");
+
 	err = arm_spe_synth_events(spe, session);
 	if (err)
 		goto err_free_queues;

-- 
2.34.1

[PATCH 4/4] perf docs: Update SPE doc to include default instructions group

[James Clark]

The instructions group is now generated by default so update the doc to
reflect this. Also explain the period/downsampling mechanism in more
detail.

Signed-off-by: James Clark <james.clark@linaro.org>
---
 tools/perf/Documentation/perf-arm-spe.txt | 14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/tools/perf/Documentation/perf-arm-spe.txt b/tools/perf/Documentation/perf-arm-spe.txt
index 37afade4f1b2..cda8dd47fc4d 100644
--- a/tools/perf/Documentation/perf-arm-spe.txt
+++ b/tools/perf/Documentation/perf-arm-spe.txt
@@ -191,14 +191,20 @@ groups:
   36 branch
   0 remote-access
   900 memory
+  1800 instructions
 
 The arm_spe// and dummy:u events are implementation details and are expected to be empty.
 
-To get a full list of unique samples that are not sorted into groups, set the itrace option to
-generate 'instruction' samples. The period option is also taken into account, so set it to 1
-instruction unless you want to further downsample the already sampled SPE data:
+The instructions group contains the full list of unique samples that are not
+sorted into other groups. To generate only this group use --itrace=i1i.
 
-  perf report --itrace=i1i
+1i (1 instruction interval) signifies no further downsampling. Rather than an
+instruction interval, this generates a sample every n SPE samples. For example
+to generate the default set of events for every 100 SPE samples:
+
+  perf report --itrace==bxofmtMai100i
+
+Other period types, for example nanoseconds (ns) are not currently supported.
 
 Memory access details are also stored on the samples and this can be viewed with:
 

-- 
2.34.1

Re: [PATCH 0/4] perf arm-spe: Improve --itrace options

[Arnaldo Carvalho de Melo]

On Mon, Sep 08, 2025 at 01:10:17PM +0100, James Clark wrote:
> Most people also want all the SPE samples (instructions group), not just
> the flagged samples that are put into the various memory groups. These
> should have been shown by default but weren't because the default
> interval type wasn't supported.
> 
> Also when looking at this, it appears that the downsampling was behaving
> in a way that would discard samples from one group but not another.
> Improve that and the warning messages.
> 
> I don't want to put fixes tags on these because it's only changing the
> defaults and the behavior, but I don't think the previous behavior was
> incorrect necessarily, just copied from tracing techs but not ideal for
> SPE.

I keep trying to find some hardware to have in my homelab to test these
series, but till then I depend on people having access to such hardware
for acks or better, tested-by, so waiting a bit for those to appear.

- Arnaldo
 
> Signed-off-by: James Clark <james.clark@linaro.org>
> ---
> James Clark (4):
>       perf arm-spe: Show instruction sample types by default
>       perf arm-spe: Downsample all sample types equally
>       perf arm-spe: Display --itrace period warnings for all sample types
>       perf docs: Update SPE doc to include default instructions group
> 
>  tools/perf/Documentation/perf-arm-spe.txt | 14 +++++---
>  tools/perf/util/arm-spe.c                 | 53 ++++++++++++++++---------------
>  2 files changed, 37 insertions(+), 30 deletions(-)
> ---
> base-commit: 75a7b9d29215c5aa813b9620f3c56817918f9f8c
> change-id: 20250908-james-perf-spe-period-4711a566cba4
> 
> Best regards,
> -- 
> James Clark <james.clark@linaro.org>
> 

Re: [PATCH 2/4] perf arm-spe: Downsample all sample types equally

[Leo Yan]

On Mon, Sep 08, 2025 at 01:10:19PM +0100, James Clark wrote:
> The various sample types that are generated are based on the same SPE
> sample, just placed into different sample type bins. The same sample can
> be in multiple bins if it has flags set that cause it to be.
> 
> Currently we're only applying the --itrace interval downsampling to the
> instruction bin, which means that the sample would appear in one bin but
> not another if it was skipped due to downsampling. I don't thing anyone
> would want or expect this, so make this behave consistently by applying
> the downsampling before generating any sample.
> 
> You might argue that the "instructions" interval type doesn't make sense
> to apply to "memory" sample types because it would be skipping every n
> memory samples, rather than every n instructions. But the downsampling
> was already not an instruction interval even for the instruction
> samples. SPE has a hardware based sampling interval, and the instruction
> interval was just a convenient way to specify further downsampling. This
> is hinted at in the warning message shown for intervals greater than 1.
> 
> This makes SPE diverge from trace technologies like Intel PT and Arm
> Coresight. In those cases instruction samples can be reduced but all
> branches are still emitted. This makes sense there, because branches
> form a complete execution history, and asking to skip branches every n
> instructions doesn't really make sense. But for SPE, as mentioned above,
> downsampling the instruction samples already wasn't consistent with
> trace technologies so we ended up with some middle ground that had no
> benefit. Now it's possible to reduce the volume of samples in all groups
> and samples won't be missing from one group but present in another.
> 
> Signed-off-by: James Clark <james.clark@linaro.org>

The reason for unifying period for all samples is reasonable to me:

Reviewed-by: Leo Yan <leo.yan@arm.com>

Re: [PATCH 0/4] perf arm-spe: Improve --itrace options

[James Clark]

On 08/09/2025 10:16 pm, Arnaldo Carvalho de Melo wrote:
> On Mon, Sep 08, 2025 at 01:10:17PM +0100, James Clark wrote:
>> Most people also want all the SPE samples (instructions group), not just
>> the flagged samples that are put into the various memory groups. These
>> should have been shown by default but weren't because the default
>> interval type wasn't supported.
>>
>> Also when looking at this, it appears that the downsampling was behaving
>> in a way that would discard samples from one group but not another.
>> Improve that and the warning messages.
>>
>> I don't want to put fixes tags on these because it's only changing the
>> defaults and the behavior, but I don't think the previous behavior was
>> incorrect necessarily, just copied from tracing techs but not ideal for
>> SPE.
> 
> I keep trying to find some hardware to have in my homelab to test these
> series, but till then I depend on people having access to such hardware
> for acks or better, tested-by, so waiting a bit for those to appear.
> 
> - Arnaldo
>   

Unfortunately I don't have any good homelab suggestions. Radxa Orion O6 
are the only not-super-expensive boards that have it, but it's not 
currently working due to some ACPI issue. AWS Gravitons also have it, 
but you currently need a metal instance so that's expensive too.

Leo should be able to have a look at this one until the hardware 
trickles down further.

Thanks
James

>> Signed-off-by: James Clark <james.clark@linaro.org>
>> ---
>> James Clark (4):
>>        perf arm-spe: Show instruction sample types by default
>>        perf arm-spe: Downsample all sample types equally
>>        perf arm-spe: Display --itrace period warnings for all sample types
>>        perf docs: Update SPE doc to include default instructions group
>>
>>   tools/perf/Documentation/perf-arm-spe.txt | 14 +++++---
>>   tools/perf/util/arm-spe.c                 | 53 ++++++++++++++++---------------
>>   2 files changed, 37 insertions(+), 30 deletions(-)
>> ---
>> base-commit: 75a7b9d29215c5aa813b9620f3c56817918f9f8c
>> change-id: 20250908-james-perf-spe-period-4711a566cba4
>>
>> Best regards,
>> -- 
>> James Clark <james.clark@linaro.org>
>>

Re: [PATCH 0/4] perf arm-spe: Improve --itrace options

[Leo Yan]

On Mon, Sep 08, 2025 at 01:10:17PM +0100, James Clark wrote:
> Most people also want all the SPE samples (instructions group), not just
> the flagged samples that are put into the various memory groups. These
> should have been shown by default but weren't because the default
> interval type wasn't supported.
> 
> Also when looking at this, it appears that the downsampling was behaving
> in a way that would discard samples from one group but not another.
> Improve that and the warning messages.
> 
> I don't want to put fixes tags on these because it's only changing the
> defaults and the behavior, but I don't think the previous behavior was
> incorrect necessarily, just copied from tracing techs but not ideal for
> SPE.
> 
> Signed-off-by: James Clark <james.clark@linaro.org>

I ran the commands below, and the results are good for me.

  ./perf report
  ./perf report --itrace=i100i
  ./perf report --itrace=i100iM
  ./perf report --itrace=i100ib
  ./perf report --itrace=i100ibM

Tested-by: Leo Yan <leo.yan@arm.com>

Re: [PATCH 0/4] perf arm-spe: Improve --itrace options

[James Clark]

On 09/09/2025 10:51 am, James Clark wrote:
> 
> 
> On 08/09/2025 10:16 pm, Arnaldo Carvalho de Melo wrote:
>> On Mon, Sep 08, 2025 at 01:10:17PM +0100, James Clark wrote:
>>> Most people also want all the SPE samples (instructions group), not just
>>> the flagged samples that are put into the various memory groups. These
>>> should have been shown by default but weren't because the default
>>> interval type wasn't supported.
>>>
>>> Also when looking at this, it appears that the downsampling was behaving
>>> in a way that would discard samples from one group but not another.
>>> Improve that and the warning messages.
>>>
>>> I don't want to put fixes tags on these because it's only changing the
>>> defaults and the behavior, but I don't think the previous behavior was
>>> incorrect necessarily, just copied from tracing techs but not ideal for
>>> SPE.
>>
>> I keep trying to find some hardware to have in my homelab to test these
>> series, but till then I depend on people having access to such hardware
>> for acks or better, tested-by, so waiting a bit for those to appear.
>>
>> - Arnaldo
> 
> Unfortunately I don't have any good homelab suggestions. Radxa Orion O6 
> are the only not-super-expensive boards that have it, but it's not 
> currently working due to some ACPI issue. AWS Gravitons also have it, 
> but you currently need a metal instance so that's expensive too.
> 
> Leo should be able to have a look at this one until the hardware 
> trickles down further.
> 
> Thanks
> James
> 

Forgot to mention that everything is available on the FVP model, but 
unless the tests are specifically written to run there, they're too 
slow. The BRBE branch stack test has been, but SPE and Coresight tests 
haven't. So not very useful either unfortunately.

>>> Signed-off-by: James Clark <james.clark@linaro.org>
>>> ---
>>> James Clark (4):
>>>        perf arm-spe: Show instruction sample types by default
>>>        perf arm-spe: Downsample all sample types equally
>>>        perf arm-spe: Display --itrace period warnings for all sample 
>>> types
>>>        perf docs: Update SPE doc to include default instructions group
>>>
>>>   tools/perf/Documentation/perf-arm-spe.txt | 14 +++++---
>>>   tools/perf/util/arm-spe.c                 | 53 +++++++++++++++ 
>>> +---------------
>>>   2 files changed, 37 insertions(+), 30 deletions(-)
>>> ---
>>> base-commit: 75a7b9d29215c5aa813b9620f3c56817918f9f8c
>>> change-id: 20250908-james-perf-spe-period-4711a566cba4
>>>
>>> Best regards,
>>> -- 
>>> James Clark <james.clark@linaro.org>
>>>
>