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Tue, 14 Oct 2025 08:04:19 -0700 (PDT) Received: from [127.0.1.1] ([59.188.211.98]) by smtp.googlemail.com with ESMTPSA id 98e67ed59e1d1-33b61a1d3cfsm16258161a91.2.2025.10.14.08.04.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Oct 2025 08:04:18 -0700 (PDT) From: Nick Chan Subject: [PATCH RESEND v8 00/21] drivers/perf: apple_m1: Add Apple A7-A11, T2 SoC support Date: Tue, 14 Oct 2025 23:02:33 +0800 Message-Id: <20251014-apple-cpmu-v8-0-3f94d4a2a285@gmail.com> Precedence: bulk X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Sven Peter Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan , Krzysztof Kozlowski , Ivaylo Ivanov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 This series adds support for the CPU PMU in the older Apple A7-A11, T2 SoCs. These PMUs may have a different event layout, less counters, or deliver their interrupts via IRQ instead of a FIQ. Since some of those older SoCs support 32-bit EL0, counting for 32-bit EL0 also need to be enabled by the driver where applicable. Patch 1 adds the DT bindings. Patch 2-7 prepares the driver to allow adding support for those older SoCs. Patch 8-12 adds support for the older SoCs. Patch 13-21 are the DT changes. Signed-off-by: Nick Chan --- Changes in v8: - Rebased on top of v6.17-rc1 - Collect Ivaylo's Tested-by - Drop #define PMCR1_COUNT_A64_EL3_0_7 - Reword reason to not initialize PMUv3 remap in EL1 - Link to v7: https://lore.kernel.org/r/20250510-apple-cpmu-v7-0-bd505cb6c520@gmail.com Changes in v7: - Fix a W=1 compile warning in apple_pmu_get_event_idx() as appearently using GENMASK() in a function prototype causes a warning in GCC. - Link to v6: https://lore.kernel.org/r/20250407-apple-cpmu-v6-0-ae8c2f225c1f@gmail.com Changes in v6: - Rebased on top of v6.15-rc1 (Conflict with FEAT_PMUv3 support for KVM on Apple Hardware) - Add patch to skip initialization of PMUv3 remap in EL1 even though not strictly needed - Include DT patches - Link to v5: https://lore.kernel.org/r/20250228-apple-cpmu-v5-0-9e124cd28ed4@gmail.com Changes in v5: - Slightly change "drivers/perf: apple_m1: Add Apple A11 Support", to keep things in chronological order. - Link to v4: https://lore.kernel.org/r/20250214-apple-cpmu-v4-0-ffca0e45147e@gmail.com Changes in v4: - Support per-implementation event attr group - Fix Apple A7 event attr groups - Link to v3: https://lore.kernel.org/r/20250213-apple-cpmu-v3-0-be7f8aded81f@gmail.com Changes in v3: - Configure PMC8 and PMC9 for 32-bit EL0 - Remove redundant _common suffix from shared functions - Link to v2: https://lore.kernel.org/r/20250213-apple-cpmu-v2-0-87b361932e88@gmail.com Changes in v2: - Remove unused flags parameter from apple_pmu_init_common() - Link to v1: https://lore.kernel.org/r/20250212-apple-cpmu-v1-0-f8c7f2ac1743@gmail.com --- Nick Chan (21): dt-bindings: arm: pmu: Add Apple A7-A11 SoC CPU PMU compatibles drivers/perf: apple_m1: Only init PMUv3 remap when EL2 is available drivers/perf: apple_m1: Support per-implementation event tables drivers/perf: apple_m1: Support a per-implementation number of counters drivers/perf: apple_m1: Support configuring counters for 32-bit EL0 drivers/perf: apple_m1: Support per-implementation PMU startup drivers/perf: apple_m1: Support per-implementation event attr group drivers/perf: apple_m1: Add Apple A7 support drivers/perf: apple_m1: Add Apple A8/A8X support drivers/perf: apple_m1: Add A9/A9X support drivers/perf: apple_m1: Add Apple A10/A10X/T2 Support drivers/perf: apple_m1: Add Apple A11 Support arm64: dts: apple: s5l8960x: Add CPU PMU nodes arm64: dts: apple: t7000: Add CPU PMU nodes arm64: dts: apple: t7001: Add CPU PMU nodes arm64: dts: apple: s800-0-3: Add CPU PMU nodes arm64: dts: apple: s8001: Add CPU PMU nodes arm64: dts: apple: t8010: Add CPU PMU nodes arm64: dts: apple: t8011: Add CPU PMU nodes arm64: dts: apple: t8012: Add CPU PMU nodes arm64: dts: apple: t8015: Add CPU PMU nodes Documentation/devicetree/bindings/arm/pmu.yaml | 6 + arch/arm64/boot/dts/apple/s5l8960x.dtsi | 8 + arch/arm64/boot/dts/apple/s800-0-3.dtsi | 8 + arch/arm64/boot/dts/apple/s8001.dtsi | 8 + arch/arm64/boot/dts/apple/t7000.dtsi | 8 + arch/arm64/boot/dts/apple/t7001.dtsi | 9 + arch/arm64/boot/dts/apple/t8010.dtsi | 8 + arch/arm64/boot/dts/apple/t8011.dtsi | 9 + arch/arm64/boot/dts/apple/t8012.dtsi | 8 + arch/arm64/boot/dts/apple/t8015.dtsi | 24 + arch/arm64/include/asm/apple_m1_pmu.h | 2 + drivers/perf/apple_m1_cpu_pmu.c | 807 +++++++++++++++++++++++-- 12 files changed, 870 insertions(+), 35 deletions(-) --- base-commit: 8f5ae30d69d7543eee0d70083daf4de8fe15d585 change-id: 20250211-apple-cpmu-5a5a3da39483 Best regards, -- Nick Chan